Semiconductor device having a ferroelectric memory and manufacturing method thereof

ABSTRACT

In a ferroelectric memory having a ferroelectric film between a gate electrode and a semiconductor substrate, dielectric breakdown of a gate insulating film is prevented and the polarization performance of the ferroelectric film is enhanced to improve the performance of a semiconductor device. In a memory cell including a field effect transistor including a control gate electrode formed over the semiconductor substrate, between the control gate electrode and a main surface of the semiconductor substrate, a paraelectric film and the ferroelectric film are formed by being stacked in this order over the main surface of the semiconductor substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2017-253646 filed onDec. 28, 2017, 2017 including the specification, drawings and abstractis incorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device and amanufacturing method thereof, and particularly to a technique which iseffective when applied to a semiconductor device used as a storageelement using a ferroelectric film and a manufacturing method thereof.

In recent years, as a semiconductor storage element operating at a lowvoltage, a ferroelectric memory using a ferroelectric material has beendeveloped. The ferroelectric memory is a nonvolatile storage element inwhich the direction of polarization of the ferroelectric material iscontrolled to cause a shift between a state where information is writtenand a state where information is erased.

As a field effect transistor which operates at a high speed and can bereduced in size, leakage current, and power consumption, a fin-typetransistor is known. The fin-type transistor (FINFET standing for FinField Effect Transistor) is a semiconductor element having, e.g., aplate-like (wall-like) pattern made of a semiconductor layer protrudingover a substrate as a channel layer and having a gate electrode formedso as to mount over the pattern.

Patent Document 1 (Specification of US Patent Application PublicationNo. 2015/0214322) describes a ferroelectric memory made of a transistorincluding a SiON layer, a HfO₂ layer, a TiN layer, and a gate electrodewhich are formed in this order over a semiconductor substrate.

RELATED ART DOCUMENT Patent Document

[Patent Document 1]

-   -   Specification of US Patent Application Publication No.        2015/0214322

SUMMARY

In a ferroelectric memory using a HfO₂ film which is a ferroelectricfilm, the crystal phase of the HfO₂ film needs to be orthorhombic.However, the orthorhombic crystal phase is a metastable phase. When anamorphous (non-crystalline) HfO₂ film is formed over a semiconductorsubstrate during a manufacturing process of a semiconductor device andthen heat treatment is performed for crystallization at a hightemperature of, e.g., about 600 to 1000° C., the crystal phase of theHfO₂ film shifts to a monoclinic crystal phase, which is a stable phase.This causes a problem in that the HfO₂ film is no longer ferroelectricbut is paraelectric, and the element does not normally operate as thestorage element.

When a voltage is applied to a gate electrode for the purpose ofapplying a positive or negative electric field to a ferroelectric filmand control polarization inversion, if an electron that has entered theferroelectric film from a semiconductor substrate is trapped in theferroelectric film, the performance of the ferroelectric filmdeteriorates. To prevent this, it can be considered to insert aninterfacial layer (block layer) under the ferroelectric film and thusinhibit the performance deterioration of a ferroelectric layer due tocharge trapping. However, when the dielectric constant of theinterfacial layer is low, a problem arises in that an electric fieldinduced in the ferroelectric film causes dielectric breakdown of theinterfacial layer, resulting in a breakdown voltage failure. In the caseof inserting a metal film between the interfacial layer and theferroelectric layer, when the electrostatic capacitance of theinterfacial layer is low, a problem arises in that an electric field isless likely to be applied to the ferroelectric layer to increase avoltage for causing polarization inversion.

Other problems and novel features of the present invention will becomeapparent from a statement in the present specification and theaccompanying drawings.

The following is a brief description of the outline of a representativeone of the embodiments disclosed in the present invention.

In a semiconductor device according to an embodiment, in a memory cellincluding a field effect transistor including a control gate electrodeformed over a semiconductor substrate, between the control gateelectrode and a main surface of the semiconductor substrate, aparaelectric film and a ferroelectric film are formed by being stackedin this order over the main surface of the semiconductor are formed.

The embodiment disclosed in the present invention can improve theperformance of the semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view showing a layout configuration of asemiconductor chip in which a semiconductor device as a first embodimentof the present invention is mounted;

FIG. 2 is a cross-sectional view showing the semiconductor device as thefirst embodiment of the present invention;

FIG. 3 is an enlarged cross-sectional view showing a portion of thesemiconductor device as the first embodiment of the present invention;

FIG. 4 is a table showing an example of conditions under which voltagesare applied to the individual portions of a selected memory cell during“Write”, “Erase”, and “Read” operations in the semiconductor device asthe first embodiment of the present invention;

FIG. 5 is a cross-sectional view illustrating a manufacturing process ofthe semiconductor device as the first embodiment of the presentinvention;

FIG. 6 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 5;

FIG. 7 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 6;

FIG. 8 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 7;

FIG. 9 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 8;

FIG. 10 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 9;

FIG. 11 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 10;

FIG. 12 is a schematic view of a microwave heating device used in themanufacturing process of the semiconductor device as the firstembodiment of the present invention;

FIG. 13 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 11;

FIG. 14 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 13;

FIG. 15 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 14;

FIG. 16 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 15;

FIG. 17 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 16;

FIG. 18 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 17;

FIG. 19 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 18;

FIG. 20 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 19;

FIG. 21 is a cross-sectional view illustrating a manufacturing processof a semiconductor device as a first modification of the firstembodiment of the present invention;

FIG. 22 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 21;

FIG. 23 is a cross-sectional view illustrating a manufacturing processof a semiconductor device as a second modification of the firstembodiment of the present invention;

FIG. 24 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 23;

FIG. 25 is a plan view showing a semiconductor device as a secondembodiment of the present invention;

FIG. 26 is a perspective view showing the semiconductor device as thesecond embodiment of the present invention;

FIG. 27 is a cross-sectional view showing the semiconductor device asthe second embodiment of the present invention;

FIG. 28 is a cross-sectional view showing the semiconductor device asthe second embodiment of the present invention;

FIG. 29 is a table showing an example of conditions under which voltagesare applied to the individual portions of a selected memory cell during“Write”, “Erase”, and “Read” operations in the semiconductor device asthe second embodiment of the present invention;

FIG. 30 is a cross-sectional view illustrating a manufacturing processof the semiconductor device as the second embodiment of the presentinvention;

FIG. 31 is a perspective view illustrating the manufacturing process ofthe semiconductor device, which is subsequent to FIG. 30;

FIG. 32 is a cross-sectional view of the semiconductor device shown inFIG. 31 along a Y-direction during the manufacturing process thereof;

FIG. 33 is a perspective view illustrating the manufacturing process ofthe semiconductor device, which is subsequent to FIG. 32;

FIG. 34 is a cross-sectional view of the semiconductor device shown inFIG. 33 along the Y-direction during the manufacturing process thereof;

FIG. 35 is a perspective view illustrating the manufacturing process ofthe semiconductor device, which is subsequent to FIG. 34;

FIG. 36 is a cross-sectional view of the semiconductor device shown inFIG. 35 along the Y-direction during the manufacturing process thereof;

FIG. 37 is a perspective view illustrating the manufacturing process ofthe semiconductor device, which is subsequent to FIG. 36;

FIG. 38 is a perspective view illustrating the manufacturing process ofthe semiconductor device, which is subsequent to FIG. 37;

FIG. 39 is a cross-sectional view of the semiconductor device shown inFIG. 38 along the Y-direction during the manufacturing process thereof;

FIG. 40 is a perspective view illustrating the manufacturing process ofthe semiconductor device, which is subsequent to FIG. 39;

FIG. 41 is a cross-sectional view of the semiconductor device shown inFIG. 40 along the Y-direction during the manufacturing process thereof;

FIG. 42 is a perspective view illustrating the manufacturing process ofthe semiconductor device, which is subsequent to FIG. 41;

FIG. 43 is a cross-sectional view of the semiconductor device shown inFIG. 42 along the Y-direction during the manufacturing process thereof;

FIG. 44 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 43;

FIG. 45 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 44;

FIG. 46 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 45;

FIG. 47 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 46;

FIG. 48 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 47;

FIG. 49 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 48;

FIG. 50 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 49;

FIG. 51 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 50;

FIG. 52 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 51;

FIG. 53 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 52;

FIG. 54 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 53;

FIG. 55 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 54;

FIG. 56 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 55;

FIG. 57 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 56;

FIG. 58 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 57;

FIG. 59 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 58;

FIG. 60 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 59;

FIG. 61 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 60;

FIG. 62 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 61;

FIG. 63 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 62;

FIG. 64 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 63;

FIG. 65 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 64;

FIG. 66 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 65;

FIG. 67 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 66;

FIG. 68 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 67;

FIG. 69 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 68;

FIG. 70 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 69;

FIG. 71 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 70;

FIG. 72 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 71;

FIG. 73 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 72;

FIG. 74 is a cross-sectional view illustrating the manufacturing processof the semiconductor device, which is subsequent to FIG. 73; and

FIG. 75 is a cross-sectional view illustrating a manufacturing processof a semiconductor device as a comparative example.

DETAILED DESCRIPTION

The following will describe the embodiments of the present invention indetail on the basis of the drawings. Note that, throughout all thedrawings for illustrating the embodiments, members having the samefunctions are designated by the same reference numerals, and a repeateddescription thereof is omitted. Also, in the following embodiments, adescription of the same or like parts will not be repeated in principleunless particularly necessary.

First Embodiment

<Example of Layout Configuration of Semiconductor Chip>

Referring to FIGS. 1 to 4, a description will be given of asemiconductor device having a ferroelectric memory, which is anonvolatile memory, in the present first embodiment. FIG. 1 is aschematic view showing an example of a layout configuration of asemiconductor chip in which the semiconductor device in the presentfirst embodiment is mounted. FIG. 2 is a cross-sectional view showingthe semiconductor device as the present first embodiment. FIG. 3 is anenlarged cross-sectional view showing a portion of the semiconductordevice as the present first embodiment. FIG. 4 is a table showing anexample of conditions under which voltages are applied to the individualportions of a selected memory cell during “Write”, “Erase”, and “Read”operations in the semiconductor device as the present first embodiment.

First, a description will be given of the layout configuration of thesemiconductor device (semiconductor chip) in which a system includingthe nonvolatile memory is formed. In FIG. 1, a semiconductor chip CHPhas a CPU (Central Processing Unit) CC1, a RAM (Random Access Memory)CC2, and an analog circuit CC3. The semiconductor chip CHP also has anEEPROM (Electrically Erasable Programmable Read Only Memory) CC4, aferroelectric memory CC5, and an I/O (Input/Output) circuit CC6 to formthe semiconductor device.

The CPU (circuit) CC1 is referred to also as a central processing unit,reads an instruction from a storage device, decodes the instruction, andperforms various arithmetic operations, control, and the like on thebasis of the instruction.

The RAM (circuit) CC2 is a memory from which information stored thereincan be read randomly, i.e., as required and in which information to bestored can be newly written. The RAM CC2 is referred to also as arandomly writable/readable memory. As the RAM, a SRAM (Static RAM) usinga static circuit is used.

The analog circuit CC3 processes signals of a voltage and a currentwhich temporally continuously vary, i.e., analog signals. The analogcircuit CC3 includes, e.g., an amplification circuit, a conversioncircuit, a modulation circuit, an oscillation circuit, a power supplycircuit, and the like.

The EEPROM CC4 and the ferroelectric memory CC5 are among nonvolatilememories in which information stored therein are electrically rewritableby a write operation and an erase operation and are referred to also aselectrically erasable and programmable read only memories. Each ofmemory cells in the EEPROM CC4 includes, e.g., a storage (memory) MONOS(Metal Oxide Nitride Oxide Semiconductor) transistor, a storage (memory)MNOS (Metal Nitride Oxide Semiconductor) transistor, or the like. In theEEPROM CC4, various frequently rewritten data is stored. The EEPROM CC4or the ferroelectric memory CC5 has not only a memory cell array inwhich a plurality of nonvolatile memory cells are arranged in rows andcolumns, but also an address buffer, a row decoder, a column decoder, averify sense amplifier circuit, a sense amplifier circuit, a writecircuit, and the like.

The I/O circuit CC6 is an input/output circuit intended to perform dataoutput from inside the semiconductor chip CHP to an external devicecoupled to the semiconductor chip CHP, data input from the externaldevice coupled to the semiconductor chip CHP into the semiconductorchip, and the like.

The semiconductor device in the present first embodiment has a memorycell region and a logic circuit region. In the memory cell region, thememory cell array in which the plurality of nonvolatile memory cells arearranged in rows and columns is formed. In the logic circuit region, theCPU CC1, the RAM CC2, the analog circuit CC3, and the I/O circuit CC6 aswell as the address buffer, the row decoder, the column decoder, theverify sense amplifier circuit, the sense amplifier circuit, the writecircuit, and the like of the EEPROM CC4 or the ferroelectric memory CC5are formed.

<Structure of Semiconductor Device>

FIG. 2 shows a memory cell MC1 and an n-type transistor Q1 in thepresent first embodiment. The left part of FIG. 2 shows a memory cellregion MR where the memory cell MC included in the nonvolatile memory,which is the ferroelectric memory, is formed. The right part of FIG. 2shows a logic circuit region (peripheral circuit region) LR where then-type transistor Q1, which is an n-type MISFET (Metal InsulatorSemiconductor Field Effect Transistor or MIS field effect transistor),is formed. Peripheral circuits refer to the circuits other than thenonvolatile memory. The peripheral circuits include the control circuit,the sense amplifier, the column decoder, the row decoder, theinput/output circuit for data exchange to/from the outside of a memorymodule, the power supply circuit, and the like inside the memory moduleand include a processor such as the CPU, various analog circuits, a SRAM(Static Random Access Memory) memory module, an external input/outputcircuit, and the like outside the memory module. The n-type transistorformed in the logic circuit region LR is a lower-breakdown-voltageMISFET driven with a voltage lower than that used to drive the memorycell MC1.

The memory cell MC1 formed in the memory cell region MR is formed in,e.g., the ferroelectric memory CC5 of FIG. 1. The n-type transistor Q1in the logic circuit region LR is formed in, e.g., the RAM CC2, the CPUCC1, or the like.

In the present first embodiment, a description will be given of the casewhere, as the transistor included in the memory cell MC1 in the memorycell region MR, the n-channel MISFET is formed. However, it is alsopossible to invert the conductivity type and form a p-channel MISFET inthe memory cell region MR. Likewise, in the present first embodiment, adescription will be given of the case where the n-channel MISFET isformed in the logic circuit region LR. However, it is also possible toinvert the conductivity type and form a p-channel MISFET in the logiccircuit region LR. It is also possible to form both of an n-channelMISFET and a p-channel MISFET, i.e., a CMISFET (Complementary MISFET) inthe logic circuit region LR.

As shown in FIG. 2, the semiconductor device in the present firstembodiment has a semiconductor substrate (semiconductor wafer) SB madeof p-type monocrystalline silicon (Si) having a specific resistance of,e.g., about 1 to 10 Ωcm or the like. The semiconductor substrate SBincludes a main surface (upper surface) and a back surface (lowersurface) opposite to the main surface. The memory cell MC1 and then-type transistor Q1 are formed in the main surface of the semiconductorsubstrate SB. In the main surface of the semiconductor substrate SB, aplurality of trenches are formed and, in the trenches, isolation regionsEI made of an insulating film defining active regions are formed. Theisolation regions EI are provided so as to electrically isolateindividual elements from each other between the individual regionsarranged along the main surface of the semiconductor substrate SB. Ineach of the memory cell region MR and the logic circuit region LR also,the isolation regions EI are provided so as to electrically isolate aplurality of elements from each other.

The isolation regions EI are made of an insulator such as silicon oxideand formed by, e.g., a STI (Shallow Trench Isolation) method, a LOCOS(Local Oxidation of Silicon) method, or the like. The isolation regionsEI are formed herein by the STI method.

The memory cell MC1 in the ferroelectric memory formed in the memorycell region MR is a nonvolatile storage element including a control gateelectrode CG1 formed over the semiconductor substrate SB via amulti-layer film including a paraelectric film HK1, a ferroelectric filmHK2, and a metal film MF1 which are formed in this order and a pair ofsource and drain regions formed in the upper surface of thesemiconductor substrate SB located lateral to the control gate electrodeCG1. In the main surface of the semiconductor substrate SB under thememory cell MC1, a p-type well PW1 is formed in which a p-type impurity(e.g., B (boron)) is introduced at a relatively low concentration. Thecontrol gate electrode CG1 is made of, e.g., a polysilicon film.

Each of the foregoing pair of source and drain regions has an extensionregion EX1 which is an n⁻-type semiconductor region in which an n-typeimpurity (e.g., As (arsenic), P (phosphorus), or both of As and P) isintroduced at a relatively low concentration. The extension regions EX1,diffusion regions D1, and the p-type well PW1 are each formed to extendfrom the main surface (upper surface) of the semiconductor substrate SBto respective points at the middle of the depth of the semiconductorsubstrate SB. The depth of the p-type well PW1 is larger than therespective depths of the extension regions EX1, the diffusion regionsD1, and the isolation regions EI. Each of the foregoing pair of sourceand drain regions has the diffusion region (diffusion layer) D1 which isan n⁺-type semiconductor region in which an n-type impurity (e.g., As(arsenic) or both of As and P) is introduced at a relatively highconcentration.

Thus, each of the foregoing pair of source and drain regions has notonly the diffusion region D1 where the n-type impurity concentration ishigher, but also the extension region EX1 where the impurityconcentration is lower than in the diffusion region D1. In other words,each of the foregoing pair of source and drain regions has an LDD(Lightly doped Drain) structure. In each of the pair of source and drainregions, the extension region EX1 is formed at a position closer to thecontrol gate electrode CG1 than the position of the diffusion region D1.Specifically, the extension region EX1 and the diffusion region D1 areformed in the main surface of the semiconductor substrate SB, and theextension region EX1 is disposed between the diffusion region D1 and themain surface of the semiconductor substrate SB immediately below thecontrol gate electrode CG1. The extension region EX1 is formed shallowerthan the diffusion region D1 herein, but may also be formed deeper thanthe diffusion region D1.

When the depth is mentioned in the present invention with regard to asemiconductor region formed in the main surface (upper surface) of thesemiconductor substrate SB, the depth refers to a distance in adirection (height direction, depth direction, perpendicular direction,or vertical direction) perpendicular to the main surface of thesemiconductor substrate SB, which is the distance from the upper surfaceof the semiconductor substrate SB to the lower surface of thesemiconductor region at a lowest position (closer to the back surface ofthe semiconductor substrate SB).

In the channel length direction of the MISFET included in the memorycell MC1, the both side surfaces of a multi-layer film including theparaelectric film HK1, the ferroelectric film HK2, the metal film MF1,and the control gate electrode CG1 are in contact with respectivesidewall spacers SW each made of an insulating film. Each of thesidewall spacers SW is made of a multi-layer film including, e.g., asilicon nitride film and a silicon oxide film. Between the foregoingmulti-layer film and the sidewall spacers SW, offset spacers each madeof, e.g., a silicon nitride film, a silicon oxide film, or a multi-layerfilm thereof may also be formed. The respective upper surfaces of thecontrol gate electrode CG1 and the diffusion regions D1 are exposed fromthe sidewall spacers SW.

The lower-breakdown-voltage n-type transistor Q1 includes a gateelectrode GE formed over the main surface of the semiconductor substrateSB via a gate insulating film GI and the pair of source and drainregions formed in the main surface of the semiconductor substrate SBlocated lateral to the gate electrode GE. Similarly to the source anddrain regions formed in the memory cell region MR, the source and drainregions have extension regions EX2 which are n⁻-type semiconductorregions and diffusion regions D2 which are n⁺-type semiconductor regionseach having an impurity concentration higher than that of each of theextension regions EX2. The extension regions EX2 and the diffusionregions D2 are formed in the main surface of the semiconductor substrateSB, and the extension regions EX2 are disposed between the diffusionregions D2 and the main surface of the semiconductor substrate SBimmediately below the gate electrode GE.

The gate insulating film GI has a thickness of, e.g., about 2 nm and ismade of, e.g., a silicon oxide film. For example, the gate electrode GEis made of a polysilicon film. The both side surfaces of the gateelectrode GE of the n-type transistor Q1 in the channel length directionare covered with the respective sidewall spacers SW. The sidewallspacers SW expose the upper surface of the gate electrode GE and theupper surfaces of the diffusion regions D2. In the main surface of thesemiconductor substrate SB under the n-type transistor Q1, a p-type wellPW2 is formed in which a p-type impurity (e.g., B (boron)) is introducedat a relatively low concentration is formed. The depth of the p-typewell PW2 is larger than the respective depths of the extension regionsEX2, the diffusion regions D2, and the isolation regions EI.

Since the lower-breakdown-voltage n-type transistor Q1 is an elementrequired to operate at a high speed, the gate length of the gateelectrode GE is relatively small and the thickness of the gateinsulating film GI is relatively small.

The respective thicknesses of the control gate electrode CG1 and thegate electrode GE are equal, but the height of the upper surface of thecontrol gate electrode CG1 is larger than the height of the uppersurface of the gate electrode GE. This is because, between the gateelectrode GE and the semiconductor substrate SB, only one silicon oxidefilm is provided as the gate insulating film GI while, between thecontrol gate electrode CG1 and the semiconductor substrate SB, themulti-layer film including the paraelectric film HK1, the ferroelectricfilm HK2, and the metal film MF1 is formed. Note that the paraelectricfilm HK1 and the ferroelectric film HK2 have the function of the gateinsulating film. The height mentioned herein refers to a distance in theheight direction, which is the distance from the main surface of thesemiconductor substrate SB unless particularly described otherwise.

The respective upper surfaces of the control gate electrode CG1 and thediffusion regions D1 in the memory cell region MR and the gate electrodeGE and the diffusion regions D1 in the logic circuit region LR arecovered with silicide layers S1. Each of the silicide layers S1 is madeof, e.g., a cobalt silicide layer, a nickel silicide layer, a nickelplatinum silicide layer, or the like.

Over the semiconductor substrate SB, an interlayer insulating film IL isformed to cover the memory cell MC1 and the n-type transistor Q1. Theinterlayer insulating film IL is made mainly of, e.g., a silicon oxidefilm and has a planarized upper surface. The thickness of the interlayerinsulating film IL is larger than the thickness of a multi-layer filmincluding the paraelectric film HK1, the ferroelectric film HK2, themetal film MF1, the control gate electrode CG1, and the silicide layerS1. The interlayer insulating film IL covers the control gate electrodeCG1, the gate electrode GE, and the silicide layers S1 over therespective upper surfaces thereof.

To the respective upper surfaces of the control gate electrode CG1 andthe pair of diffusion regions D1, plugs (contact plugs) CP are coupledvia the silicide layers S1. The plugs CP are coupling metal films(conductive coupling portions) extending through the interlayerinsulating film IL. In FIG. 1, the plug electrically coupled to thecontrol gate electrode CG1 is not shown, but is formed in anotherregion.

Likewise, to the respective upper surfaces of the gate electrode GE andthe pair of diffusion regions D2, the plugs CP are coupled via thesilicide layers S1. In FIG. 1, the plug electrically coupled to the gateelectrode GE is not shown, but is formed in another region.

Each of the plurality of plugs CP is made mainly of, e.g., W (tungsten).It is conceivable that the plug CP includes a main conductor film madeof W (tungsten) and a barrier conductor film covering the side andbottom surfaces of the main conductor film. However, in the drawing, theillustration of a multi-layer structure including the main conductorfilm and the barrier conductor film is omitted, and the plug CP is shownas one conductor film. Note that, as the material of the barrierconductor film, e.g., TiN (titanium nitride) can be used.

Over the interlayer insulating film IL and the plugs CP, an interlayerinsulating film (not shown) is additionally formed. The interlayerinsulating film is made mainly of, e.g., a silicon oxide film. Theinterlayer insulating film has a plurality of wire trenches extendingfrom the upper surface thereof to the lower surface thereof. In each ofthe wire trenches, a wire M1 is embedded. The wire M1 is made mainly of,e.g., Cu (copper) and formed by, e.g., a so-called single damascenemethod. The upper surfaces of the wires M1 and the upper surface of theinterlayer insulating film are planarized to be generally flush witheach other. The interlayer insulating film and the plurality of wires M1are included in the first wiring layer. The first wiring layer islocated above the main surface of the semiconductor substrate SB andclosest to the main surface of the semiconductor substrate SB.

The bottom surfaces of the wires M1 are coupled to the upper surfaces ofthe plugs CP. Consequently, the wires M1 are electrically coupled to thecontrol gate electrode CG1, the gate electrode GE, and the source anddrain regions via the plugs CP and the silicide layers S1. Note that thewires M1 electrically coupled respectively to the control gate electrodeCG1 and the gate electrode GE are formed in another region not shown inFIG. 1.

The paraelectric film HK1 used herein has a dielectric constant(relative permittivity) higher than that of SiN (silicon nitride). Inshort, the paraelectric film HK1 is a so-called high-k film. Theparaelectric film HK1 is an insulating film made of a material in whichdielectric polarization occurs when an electric field is applied theretoand the dielectric polarization is reduced to zero when the electricfield is removed therefrom, i.e., a paraelectric material. Specifically,in the paraelectric film HK1, unlike in a ferroelectric material, nopolarization remains in the absence of the applied electric field. Theparaelectric film HK1 is made of, e.g., HfSiO₄ (hafnium silicate), HfO₂(hafnia), or ZrO₂ (zirconia). In the paraelectric film HK1, an impuritysuch as Zr (zirconium), Si (silicon), N (nitrogen), C (carbon), or F(fluorine) may also be introduced. The thickness of the paraelectricfilm HK1 is, e.g., 2 nm.

The paraelectric film HK1 has a polycrystalline structure, which is acrystal structure (crystal phase) other than an orthorhombic crystalstructure. Specifically, examples of the crystal structure of a filmcontaining Hf or Zr include an orthorhombic crystal structure, amonoclinic crystal structure, and a tetragonal crystal structure, andthe crystal structure of the paraelectric film HK1 is not theorthorhombic crystal structure, but the monoclinic crystal structure orthe tetragonal crystal structure. Even if some of a large number ofcrystal grains included in the paraelectric film HK1 have theorthorhombic crystal structures, the ratio of the volume of theorthorhombic crystal grains to the unit volume of the paraelectric filmHK1 is less than 50%. In other words, 50% or more of the large number ofcrystal grains included in the paraelectric film HK1 have crystalstructures other than the orthorhombic crystal structure. This meansthat the main crystal phase of the plurality of crystal grains includedin the paraelectric film HK1 is the monoclinic crystal phase, thetetragonal crystal phase, or both of the monoclinic crystal phase andthe tetragonal crystal phase. In other words, 50% or more of the largenumber of crystal grains included in the paraelectric film HK1 havecrystal structures other than the orthorhombic crystal structure. In thepresent invention, a high-k film made mainly of crystals other than anorthorhombic crystal is referred to as a paraelectric film.

The ferroelectric film HK2 is a film having a dielectric constant(relative permittivity) higher than that of each of SiN (siliconnitride) and a paraelectric material. In other words, the ferroelectricfilm HK2 is neither a SiN film nor an insulating film having adielectric constant lower than that of the SiN film. In short, theferroelectric film HK2 is a so-called high-k film and the dielectricconstant (relative permittivity) of the ferroelectric film HK2 is higherthan the dielectric constant (relative permittivity) of the paraelectricfilm HK1. The ferroelectric film HK2 is an insulating film made of amaterial in which dielectric polarization occurs when an electric fieldis applied thereto and the polarization is not reduced to zero even whenthe electric field is removed therefrom, i.e., a dielectric material.Specifically, in the ferroelectric film HK2, unlike in a paraelectricmaterial, the polarization remains even in the absence of the appliedelectric field. In the ferroelectric material, electric dipoles arealigned even in the absence of an external electric field, and thedirections of the dipoles can be changed using an electric field.

To allow a high-k film to serve as a ferroelectric film, it is necessaryfor the high-k film to have an orthorhombic crystal phase. In otherwords, the high-k film formed mainly of crystals having the crystalphases other than the orthorhombic crystal phase is a paraelectric film.Accordingly, in a ferroelectric memory, to increase residualpolarization in a ferroelectric film, improve the performance of aferroelectric material, and reduce a drive power for the ferroelectricmemory, it is necessary to maximize the ratio of orthorhombic crystalsto all the crystals included in the ferroelectric film.

The ferroelectric film HK2 is made of, e.g., HfSiO₄ (hafnium silicate),HfO₂ (hafnia), or HfZrO₂ (hafnium zirconium dioxide). In short, theferroelectric film HK2 is a hafnium oxide (Hf_(X)O_(Y)) film. In theferroelectric film HK2, an impurity such as Zr (zirconium), Si(silicon), N (nitrogen), C (carbon), or F (fluorine) may be introduced.Specifically, the ferroelectric film HK2 includes, e.g., HfO₂ and animpurity (such as, e.g., Zr or Si) which are mixed at a 1:1 ratio. Theimpurity concentration of the ferroelectric film HK2 is, e.g., 50%. Theconcentration (impurity concentration) of the impurity (Zr, Si, N, C, orF) in the ferroelectric film HK2 is higher than the concentration(impurity concentration) of the impurity (Zr, Si, N, C, or F) in theparaelectric film HK1.

The thickness of the ferroelectric film HK2 is, e.g., 10 to 20 nm. Thus,the thickness of the ferroelectric film HK2 is larger than the thicknessof the paraelectric film HK1. This allows an electric field (gateelectric field) generated by applying a voltage to the control gateelectrode CG1 to be more easily applied to the ferroelectric film HK2.Specifically, when the ferroelectric film HK2 is formed thicker than theparaelectric film HK1, the gate electric field is concentrated on theferroelectric film HK2 so that the ferroelectric film HK2 is more easilypolarized. This can reduce the operating voltage of the memory cell MC1.

The ferroelectric film HK2 has a polycrystalline structure, which is anorthorhombic crystal structure (crystal phase). Even if some of a largenumber of crystal grains included in the ferroelectric film HK2 havecrystal structures other than the orthorhombic crystal structure, theratio of the volume of the crystal grains other than orthorhombiccrystal grains to the unit volume of the ferroelectric film HK2 is lessthan 50%. In other words, 50% or more of the large number of crystalgrains included in the ferroelectric film HK2 have the orthorhombiccrystal structures. In short, the ferroelectric film mentioned in thepresent invention is a high-k film made mainly of orthorhombic crystals.

The metal film MF1 is a conductive film made of, e.g., a TiN (titaniumnitride) film. The thickness of the metal film MF1 is, e.g., 10 to 20nm. The metal film MF1 is a cap film provided so as to give a stress tothe ferroelectric film HK2. In the process of manufacturing theferroelectric memory, a HfO₂ film deposited in a non-crystalline(amorphous) state is heated to thus form the ferroelectric film HK2 madeof the crystallized HfO₂ film. At this time, the heating is performedwith the metal film MF1 being formed over the amorphous HfO₂ film toincrease the likelihood of formation of orthorhombic crystal grains inthe ferroelectric film HK2. Specifically, by forming the metal film MF1,the ratio of the orthorhombic crystal grains to all the crystal grainsincluded in the ferroelectric film HK2 is increased to thus allow theferroelectric film HK2 to be polarized at a low voltage. This can reducethe power consumption of the memory cell MC1.

The paraelectric film HK1 is an interfacial layer (block layer) providedto prevent electrons from being trapped (captured) in the gateinsulating film including the ferroelectric film HK2. When theferroelectric memory is operated, a voltage may be applied to thecontrol gate electrode to apply a positive or negative electric field tothe ferroelectric film and control the polarization inversion of theferroelectric film. In that case, electrons may enter the ferroelectricfilm from the semiconductor substrate. When charges are consequentlytrapped in the gate insulating film including the ferroelectric film,the performance of the ferroelectric film deteriorates.

Specifically, when a positive voltage is applied to the control gateelectrode to bring the memory cell including the transistor in theferroelectric memory into an erased state (state where the thresholdvoltage of the transistor is low), charges are trapped in the gateinsulating film to increase the threshold voltage of the transistor.Conversely, when a negative voltage is applied to the control gateelectrode to bring the memory cell into a written state (state where thethreshold voltage of the transistor is high), the charges trapped in thegate insulating film are extracted therefrom to reduce the thresholdvoltage of the transistor. As a result, the charges trapped in the gateinsulating film may prevent the ferroelectric memory from normallyoperating.

To prevent charges from being thus trapped, in the present firstembodiment, the paraelectric film HK1 is formed as the interfacial layer(block layer) between the ferroelectric film HK2 and the semiconductorsubstrate SB which are shown in FIG. 2. This can prevent charges frombeing trapped in the gate insulating film including the paraelectricfilm HK1 and the ferroelectric film HK2. As a result, it is possible toprevent the performance of the ferroelectric film HK2 fromdeteriorating.

Next, using FIG. 3, a description will be given of a specificconfiguration of the paraelectric film HK1 and the ferroelectric filmHK2. FIG. 3 shows the respective polycrystalline structures of theparaelectric film HK1 and the ferroelectric film HK2 in enlargedrelation. The illustration of a structure (including the control gateelectrode, the sidewall spacers, the interlayer insulating film, and thelike) above the ferroelectric film HK2 is omitted.

As shown in FIG. 3, the paraelectric film HK1 includes a plurality ofcrystals GR1, while the ferroelectric film HK2 includes a plurality ofcrystals GR2. The diameter (grain diameter) of each of the crystals GR1is, e.g., 1 to 2 nm, while the diameter (grain diameter) of each of thecrystals GR2 is, e.g., 5 to 10 nm. In other words, the average graindiameter of the crystals GR2 included in the ferroelectric film HK2 islarger than the average grain diameter of the crystals GR1 included inthe paraelectric film HK1. The respective grain diameters and heights ofthe plurality of crystals GR1 are varied, and the respective graindiameters and heights of the plurality of crystals GR2 are also varied.Accordingly, each of the upper surfaces of the paraelectric film HK1 andthe ferroelectric film HK2 has unevenness. Since the grain diameters ofthe crystals GR2 included in the ferroelectric film HK2 are larger thanthe grain diameters of the crystals GR1 included in the paraelectricfilm HK1, the unevenness (roughness) of the upper surface of theferroelectric film HK2 is larger than the unevenness (roughness) of theupper surface of the paraelectric film HK1.

One reason for the size difference between the crystals GR1 and GR2 isthat the ferroelectric film HK2 is formed to have a thickness largerthan that of the paraelectric film HK1. Another reason is that the graindiameters of the crystals GR2 are set large to thus improve thepolarization property of the ferroelectric film HK2. Ideally, theferroelectric film HK2 preferably includes only single crystals.However, since it is difficult to form single crystals, theferroelectric film HK2 is formed as a polycrystalline film. Since nopolarization occurs in the boundary region (crystal grain boundary)between the adjacent crystals GR2, the number of the crystal grainboundaries is preferably minimized.

Accordingly, in the present first embodiment, the crystals GR2 areformed larger than the crystals GR1 to reduce the number of the crystalgrain boundaries. By increasing the crystal grain diameters, theplurality of crystals GR2 included in the ferroelectric film HK2 aremore likely to be polarized in equal directions. This can increaseresidual polarization after the application of the voltage to theferroelectric film HK2. The residual polarization is the size ofpolarization remaining in the ferroelectric film HK2 when the electricfield applied to the ferroelectric film HK2 is zero. By increasing theresidual polarization in the ferroelectric film HK2, it is possible toreduce the operating voltage of the ferroelectric memory and improve aninformation retention property in the ferroelectric memory.

<Operations in Semiconductor Device>

Next, a description will be given of an example of operations in thenonvolatile memory with reference to FIG. 4.

FIG. 4 is a table showing an example of conditions under which voltagesare applied to the individual portions of a selected memory cell during“Write”, “Erase”, and “Read” operations. In the table of FIG. 4, avoltage Vd applied to the drain region of the memory cell (selectedmemory cell) MC1 shown in FIG. 2, a voltage Vg applied to the controlgate electrode CG1 thereof, a voltage Vs applied to the source regionthereof, and a voltage Vb applied to the p-type well PW1 thereof duringeach of the “Write”, “Erase”, and “Read” operations are shown. Note thatwhat is shown in the table of FIG. 4 is a preferred example of theconditions for voltage application. The conditions for voltageapplication are not limited thereto, and can variously be changed asnecessary. In the present first embodiment, bringing the memory cell MC1into the state where the ferroelectric film HK2 is upwardly polarizedand the threshold voltage of the transistor included in the memory cellMC1 is relatively high is defined as the “Write” operation. On the otherhand, bringing the memory cell MC1 into the state where theferroelectric film HK2 is downwardly polarized and the threshold voltageof the transistor included in the memory cell MC1 is relatively low isdefined as the “Erase” operation”.

In the present first embodiment, the “Write” operation to the memorycell MC1 is performed by applying a negative voltage to the control gateelectrode CG1 thereof. Specifically, such voltages as shown in, e.g.,the “Write” row in FIG. 4 are applied to the individual portions of theselected memory cell to which the “Write” operation is performed. Thus,the ferroelectric film HK2 of the selected memory cell is upwardlypolarized to effect the “Write” operation. This increases the thresholdvoltage of the transistor included in the memory cell MC1. As a result,the memory cell MC1 is brought into the written state.

In the present first embodiment, the “Erase” operation to the memorycell MC1 is performed by applying a positive voltage to the control gateelectrode CG1 thereof. Specifically, such voltages as shown in the“Erase” row in FIG. 4 are applied to the individual portions of theselected memory cell to which the “Erase” operation is performed. Thus,the ferroelectric film HK2 of the selected memory cell is downwardlypolarized to effect the “Erase” operation. This reduces the thresholdvoltage of the transistor included in the memory cell MC1. As a result,the memory cell MC1 is brought into the erased state.

When the “Read” operation is performed, such voltages as shown in, e.g.,the “Read” row in FIG. 4 are applied to the individual portions of theselected memory cell to which the “Read” operation is performed. Bysetting the voltage Vg to be applied to the control gate electrode CG1during the “Read” operation to a value between the threshold voltage ofthe foregoing transistor in the written state and the threshold voltageof the foregoing transistor in the erased state, the written state orthe erased state can be determined.

<Effects of Semiconductor Device>

Next, using FIG. 75, a description will be given of the effects of thesemiconductor device in the present first embodiment. FIG. 75 is across-sectional view showing a memory cell MCA in a ferroelectric memoryas a semiconductor device in a comparative example.

A structure of the memory cell MCA in the comparative example shown inFIG. 75 is mainly different from that of the memory cell in the presentfirst embodiment in that, between the ferroelectric film HK2 and thesemiconductor substrate SB, an insulating film IFC, which is neither aferroelectric film nor a paraelectric film, is formed. The insulatingfilm IFC is made of, e.g., a silicon oxide film or a silicon nitridefilm. Specifically, the dielectric constant (relative permittivity) ofthe insulating film IFC is not more than that of silicon nitride so thatthe insulating film IFC is not a high-k film.

As described above, in the ferroelectric memory including thetransistors, to prevent charges from being trapped in the gateinsulating film including the ferroelectric film, it can be consideredto form the interfacial layer (block layer) between the ferroelectricfilm and the semiconductor substrate. Accordingly, in the comparativeexample, the insulating film IFC made of, e.g., a silicon nitride filmis provided under the ferroelectric film HK2 to be interposed betweenthe semiconductor substrate and the ferroelectric film HK2. However,when the insulating film IFC as the interfacial layer is made of amaterial having a low dielectric constant such as silicon nitride orsilicon oxide, a problem arises in that the electric field induced inthe ferroelectric film HK2 causes dielectric breakdown of theinterfacial layer, resulting in a breakdown voltage failure.

By contrast, in the present first embodiment, as shown in FIG. 2, theparaelectric film HK1 is formed as the interfacial layer. By thusforming the paraelectric film HK1 made of a material having a dielectricconstant (relative permittivity) higher than that of silicon nitride, itis possible to prevent the electric field induced in the ferroelectricfilm HK2 from causing dielectric breakdown of the interfacial layer.Therefore, it is possible to improve the reliability of thesemiconductor device.

Also, in the present first embodiment, as described using FIG. 3, thecrystals GR2 are formed larger than the crystals GR1 to allow theresidual polarization in the ferroelectric film HK2 to be increased.This can reduce the operating voltage of the ferroelectric memory andimprove the information retention property in the ferroelectric memory.As a result, it is possible to improve the performance of thesemiconductor device.

As an approach taken to form the crystals GR2 larger than the crystalsGR1, the paraelectric film HK1 is formed under the ferroelectric filmHK2 to come in contact with the lower surface of the ferroelectric filmHK2. In the case where the interfacial layer is formed of theparaelectric film HK1, when the ferroelectric film HK2 is formed overthe upper surface of the interfacial layer, crystal nuclei are lesslikely to be formed in the ferroelectric film HK2 than in the case wherethe interfacial layer is formed of a silicon nitride film, a siliconoxide film, or the like. As a result, the number of the crystals GR2included in the ferroelectric film HK2 is reduced. This allows each ofthe crystals GR2 to grow large without being inhibited from growing bythe adjacent crystals GR2. Thus, by forming the paraelectric film HK1 asthe interfacial layer under the ferroelectric film HK2, the crystals GR2included in the ferroelectric film HK2 can be formed large.

<Manufacturing Process of Semiconductor Device>

Using FIGS. 5 to 20, the following will describe a method ofmanufacturing the semiconductor device in the present first embodiment.FIGS. 5 to 20 are cross-sectional views of the semiconductor device inthe present first embodiment during the formation process thereof. FIGS.5 to 20 show the memory cell region MR and the logic circuit region LRwhich are arranged in this order in a left-to-right direction.

First, as shown in FIG. 5, the semiconductor substrate SB is providedherein. The semiconductor substrate SB is made of p-type monocrystallinesilicon having a specific resistance of, e.g., about 1 to 10 Ωcm or thelike. Subsequently, in the peripheral surface of the semiconductorsubstrate SB, using a photolithographic technique and an etching method,a plurality of trenches (isolation trenches) are formed. Then, a siliconoxide film is formed using, e.g., a CVD (Chemical Vapor Deposition)method to be embedded in each of the plurality of trenches. Then, thesilicon oxide film located outside each of the plurality of trenches isremoved to form the isolation region EI left in each of the trenches.The isolation region EI is made mainly of an insulator such as siliconoxide and has, e.g., a STI structure.

Subsequently, in the memory cell region MR, using an ion implantationmethod, an impurity is introduced into the main surface of thesemiconductor substrate SB to form the p-type well PW1 as a p-typesemiconductor region extending from the main surface of thesemiconductor substrate SB to a point at the middle of the depth of thesemiconductor substrate SB. On the other hand, in the logic circuitregion LR, using an ion implantation method, an impurity is introducedinto the main surface of the semiconductor substrate SB to form thep-type well PW2 as a p-type semiconductor region extending from the mainsurface of the semiconductor substrate SB to a point at the middle ofthe depth of the semiconductor substrate SB. The p-type wells PW1 andPW2 are formed by implanting a p-type impurity (e.g., B (boron)).

Next, as shown in FIG. 6, over the main surface of the semiconductorsubstrate SB, an insulating film IFA is formed. The insulating film IFAhas a thickness of, e.g., about 2 nm and is made of, e.g., a siliconoxide film. The insulating film IFA can be formed by, e.g., an oxidationmethod such as a thermal oxidation method, a CVD method, or the like.

Next, as shown in FIG. 7, using a photolithographic technique and anetching method, the insulating film IFA is removed from the memory cellregion MR. Thus, in the main cell region MR, the main surface of thesemiconductor substrate SB is exposed.

Next, as shown in FIG. 8, over the main surface of the semiconductorsubstrate SB, a high-k film (insulating film) AM1 in a non-crystalline(amorphous) state is formed. The high-k film AM1 can be formed by, e.g.,a CVD method, a PVD (Physical Vapor Deposition) method, or an ALD(Atomic Layer Deposition) method. The thickness of the high-k film AM1is, e.g., 1 to 2 nm.

Next, as shown in FIG. 9, the high-k film AM1 is heated at about 600 to1000° C. to be crystallized (first heat treatment). Thus, theparaelectric film HK1 is formed. The thickness of the paraelectric filmHK1 is, e.g., about 1 to 2 nm. The paraelectric film HK1 has adielectric constant (relative permittivity) higher than that of siliconnitride and is made of, e.g., HfSiO₄ (hafnium silicate), HfO₂ (hafnia),or ZrO₂ (zirconia). Into the paraelectric film HK1, an impurity such asZr (zirconium), Si (silicon), N (nitrogen), C (carbon), or F (fluorine)may also be introduced.

The paraelectric film HK1 is a polycrystalline body including aplurality of crystals (crystal grains or microcrystals). The averagediameter (crystal grain diameter) of the plurality of crystals is, e.g.,1 to 2 nm. These crystals have crystal structures other than anorthorhombic crystal structure. In short, the paraelectric film HK1 is apolycrystalline film made mainly of monoclinic crystals or tetragonalcrystals. The semiconductor substrate SB is heated herein at arelatively high temperature of about 600 to 1000° C. to thus form theparaelectric film HK1. Accordingly, as the crystals included in theparaelectric film HK1, monoclinic crystals in a stable phase are likelyto be formed.

The first heat treatment can be performed using an RTA (Rapid ThermalAnnealing) method. Alternatively, the first heat treatment can beperformed by a furnace anneal process. In the furnace anneal process, aplurality of semiconductor wafers placed in a vertical furnace aresubjected to simultaneous heat treatment.

Next, as shown in FIG. 10, over the main surface of the semiconductorsubstrate SB, a high-k film (insulating film) AM2 in a non-crystalline(amorphous) state containing Hf (hafnium) is formed. In other words,over the paraelectric film HK1, the high-k film AM2 is formed. Thehigh-k film AM2 can be formed by, e.g., a CVD method, a PVD method, oran ALD method. The thickness of the high-k film AM2 is, e.g., 10 to 20nm.

Next, as shown in FIG. 11, using, e.g., a CVD method or a sputteringmethod, the metal film MF1 as the cap film is formed over the high-kfilm AM2. The metal film MF1 is made of, e.g., a TiN (titanium nitride)film and has a thickness of, e.g., 10 to 20 nm. The metal film MF1 isformed in contact with the upper surface of the high-k film AM2. Themetal film MF1 is provided so as to apply a stress to the high-k filmAM2.

Next, using the microwave heating device shown in FIG. 12, as shown inFIG. 13, the high-k film AM2 is heated at 300 to 400° C. (second heattreatment). By thus crystallizing the high-k film AM2, the ferroelectricfilm HK2 is formed. The thickness of the ferroelectric film HK2 is,e.g., 10 to 20 nm. The ferroelectric film HK2 has a dielectric constant(relative permittivity) higher than those of silicon nitride and theparaelectric film HK1 and is made of, e.g., HfSiO₄ (hafnium silicate),HfO₂ (hafnia), or HfZrO₂ (hafnium zirconium dioxide). In theferroelectric film HK2, an impurity such as Zr (zirconium), Si(silicon), N (nitrogen), C (carbon), or F (fluorine) may also beintroduced. The concentration of such an impurity in the ferroelectricfilm HK2 is higher than the concentration of the impurity (Zi, Si, N, C,or F) in the paraelectric film HK1.

The ferroelectric film HK2 is a polycrystalline body including aplurality of crystals (crystal grains). The average diameter (crystalgrain diameter) of the plurality of crystals is, e.g., 5 to 10 nm. Thecrystal grain diameters in the ferroelectric film HK2 are larger thanthe crystal grain diameters in the paraelectric film HK1. Accordingly,variations in the grain diameter of each of the plurality of crystalsincluded in the ferroelectric film HK2 are larger than variations in thegrain diameter of each of the plurality of crystals included in theparaelectric film HK1. Consequently, the unevenness (roughness) of theupper surface of the ferroelectric film HK2 is larger than theunevenness (roughness) of the upper surface of the paraelectric filmHK1.

Each of these crystals has an orthorhombic crystal structure. In short,the ferroelectric film HK2 is a polycrystalline film made mainly oforthorhombic crystals. The semiconductor substrate SB is heated hereinat a relatively low temperature of about 300 to 400° C. to thus form theferroelectric film HK2. Consequently, as the crystals included in theferroelectric film HK2, orthorhombic crystals in a metastable phase arelikely to be formed. As a result of performing the second heat treatmentin the state where a stress is applied to the high-k film AM2 from themetal film MF1 formed over the high-k film AM2 (see FIG. 11), in theferroelectric film HK2, not monoclinic crystals or tetragonal crystals,but orthorhombic crystals are likely to be formed. When a heatingtemperature in the second heat treatment is less than 300° C.,crystallization is less likely to occur so that, in the second heattreatment, the heating is performed under a temperature condition of notless than 300° C.

The microwave heating device shown in FIG. 12 includes a wafer stage STin a container and a pair of magnetrons (microwave oscillators) MGTdisposed such that the wafer stage ST is interposed therebetween in ahorizontal direction. In the second heat treatment, with a semiconductorwafer WF as the semiconductor substrate SB being placed over the waferstage ST, an oscillating electromagnetic wave (radio frequency (RF) ormicrowave) from the magnetrons MGT is applied to the semiconductor waferWF. Thus, the high-k film AM2 is heated by a heating method using thelattice vibration of crystals to form the ferroelectric film HK2. Thefrequency of the microwave applied herein is set to 1 to 10 GHz,specifically to, e.g., 2.45 GHz.

At this time, as shown in FIG. 13, a microwave having an electric fieldE which vibrates in a direction at 90 degrees (perpendicular) to themain surface of the semiconductor substrate SB is applied. In otherwords, the direction in which a magnetic field M of the microwavevibrates is along the main surface of the semiconductor substrate SB.Specifically, the microwave is caused to be incident on the high-k filmAM2 such that the direction in which the electric field E of themicrowave vibrates is perpendicular to the upper surface of the high-kfilm AM2. As a result, in the process of crystallization of the high-kfilm AM2, crystals which are polarized in the perpendicular directionare selectively heated and grown by the microwave having the electricfield E which vibrates in the perpendicular direction. Consequently, inthe ferroelectric film HK2, orthorhombic crystals polarized in theperpendicular direction are formed. Since the crystals polarized in theperpendicular direction are selectively heated by the microwave havingthe electric field E which vibrates in the perpendicular direction, thecrystallization can be achieved at a low temperature of not more than400° C.

The second heat treatment is performed herein in the state where thehigh-k film AM2 is formed over the paraelectric film HK1 having theupper surface where crystal nuclei are less likely to be formed.Accordingly, the number of the crystals included in the ferroelectricfilm HK2 is reduced. As a result, the crystals included in theferroelectric film HK2 are allowed to grow large without being inhibitedfrom growing by another adjacent crystal.

Next, as shown in FIG. 14, using a photolithographic technique and anetching method, the metal film MF1, the ferroelectric film HK2, and theparaelectric film HK1 are removed from the logic circuit LR to exposethe insulating film IFA.

Next, as shown in FIG. 15, over the main surface of the semiconductorsubstrate SB, a polysilicon film PS is formed. The polysilicon film PSis formed to cover the upper surface of the metal film MF1 in the memorycell region MR and the upper surface of the insulating film IFA in thelogic circuit region LR.

Next, as shown in FIG. 16, using a photolithographic technique and a dryetching method, the polysilicon film PS, the metal film MF1, theferroelectric film HK2, the paraelectric film HK1, and the insulatingfilm IFA are processed to thus expose the main surface of thesemiconductor substrate SB and the upper surfaces of the isolationregions EI. By this patterning step, in the memory cell region MR, thecontrol gate electrode CG1 made of the polysilicon film PS is formedand, in the logic circuit region LR, the gate electrode GE made of thepolysilicon film PS and the gate insulating film GI made of theinsulating film IFA are formed. Thus, in the memory cell region MR, amulti-layer body including the paraelectric film HK1, the ferroelectricfilm HK2, the metal film MF1, and the control gate electrode CG1 whichare stacked in this order over the main surface of the semiconductorsubstrate SB is formed. On the other hand, in the logic circuit regionLR, a multi-layer body including the gate insulating film GI and thegate electrode GE which are stacked in this order over the main surfaceof the semiconductor substrate SB is formed.

Next, as shown in FIG. 17, using the control gate electrode CG1 and thegate electrode GE as a mask (ion implantation blocking mask), ionimplantation is performed on the main surface of the semiconductorsubstrate SB. Thus, in the main surface of the semiconductor substrateSB in each of the memory cell region MR and the logic circuit region LR,the pair of extension regions EX1 as the n-type semiconductor regionsare formed. The extension regions EX1 can be formed by implanting ann-type impurity (e.g., P (phosphorus) or As (arsenic)). The extensionregions EX1 are each formed to reach a predetermined depth from the mainsurface of the semiconductor substrate SB. The depths of the extensionregions EX1 are shallower than those of the isolation regions EI and thep-type wells PW1 and PW2.

Next, as shown in FIG. 18, over the semiconductor substrate SB, aninsulating film is deposited by a CVD method or the like to cover eachof the control gate electrode CG1 and the gate electrode GE. Theinsulating film is made of a multi-layer film including, e.g., a siliconoxide film and a silicon nitride film. Subsequently, the insulating filmis partly removed using a dry etching method to expose the respectiveupper surfaces of the semiconductor substrate SB, the control gateelectrode CG1, and the gate electrode GE. Thus, the sidewall spacers SWmade of the insulating films covering the respective side surfaces ofthe control gate electrode CG1 and the gate electrode GE areself-alignedly formed.

Next, as shown in FIG. 19, using the control gate electrode CG1, thegate electrode GE, and the sidewall spacers SW as a mask (ionimplantation blocking mask), ion implantation is performed on the mainsurface of the semiconductor substrate SB. Thus, in the main surface ofthe semiconductor substrate SB in each of the memory cell region MR andthe logic circuit region LR, the pair of diffusion regions D1 as then-type semiconductor regions are formed. The diffusion regions D1 can beformed by implanting an n-type impurity (e.g., P (phosphorus) or As(arsenic)). The diffusion regions D1 are each formed to reach apredetermined depth from the main surface of the semiconductor substrateSB. The depths of the diffusion regions D1 are deeper than those of theextension regions EX1 and shallower than those of the isolation regionsEI and the p-type wells PW1 and PW2. The diffusion regions D1 haveimpurity concentrations higher than those of the extension regions EX1.

In the memory cell region MR, the pair of extension regions EX1 and thepair of diffusion regions D1 which are formed such that the control gateelectrode CG1 is interposed therebetween are included in the source anddrain regions. Specifically, the extension region EX1 and the diffusionregion D1 which are in contact with each other on one of both sides ofthe control gate electrode CG1 serve as the source region, while theextension region EX1 and the diffusion region D1 which are in contactwith each other on the other side of the control gate electrode CG1serve as the drain region. Likewise, in the logic circuit region LR, thepair of extension regions EX1 and the pair of diffusion regions D1 whichare formed such that the gate electrode GE is interposed therebetweenare included in the source and drain regions.

As a result, in the memory cell region MR, the memory cell MC1 of theferroelectric memory which includes the MISFET (MIS field effecttransistor) including the paraelectric film HK1, the ferroelectric filmHK2, the control gate electrode CG1, and the source and drain regions isformed. On the other hand, in the logic circuit region LR, the n-typetransistor Q1 which is the MISFET (MIS field effect transistor)including the gate electrode GE and the source and drain regions isformed. The paraelectric film HK1 and the ferroelectric film HK2function as the gate insulating film of the transistor included in thememory cell MC1.

Subsequently, a known salicide process is performed to form the silicidelayers S1 in the respective upper surfaces of the control gate electrodeCG1, the gate electrode GE, and the diffusion regions D1. Over thesemiconductor substrate SB, e.g., a NiPt film is deposited herein by asputtering method and then subjected to heat treatment to form thesilicide layers S1. Then, the unneeded NiPt film is removed.

Subsequently, over the main surface of the semiconductor substrate SB,an insulating film is deposited by a CVD method or the like. Then, theupper surface of the insulating film is planarized to form theinterlayer insulating film IL made of the insulating film. Theinterlayer insulating film IL is made mainly of a silicon oxide film.The interlayer insulating film IL may also have a thick silicon oxidefilm and a thin silicon nitride film (liner film) interposed between thesilicon oxide film and each of the semiconductor substrate SB, thecontrol gate electrode CG1, the gate electrode GE, the sidewall spacersSW, and the silicide layers S1. The upper surface of the interlayerinsulating film IL can be planarized by a polishing process using, e.g.,a CMP (Chemical Mechanical Polishing) method.

Next, as shown in FIG. 20, using a photolithographic technique and a dryetching method, a plurality of contact holes (coupling holes) extendingthrough the interlayer insulating film IL and exposing the respectiveupper surfaces of the plurality of silicide layers S1 are formed.Specifically, the contact holes expose the upper surfaces of thesilicide layers S1 covering the respective upper surfaces of the controlgate electrode CG1, the gate electrode GE, and the diffusion regions D1.The respective contact holes provided immediately above the control gateelectrode CG1 and the gate electrode GE are formed in a region notshown.

Subsequently, over the main surface of the semiconductor substrate SB, ametal film is formed using, e.g., a sputtering method. Thus, the metalfilm is embedded in each of the plurality of contact holes. Then,polishing is performed using a CMP method to expose the upper surface ofthe interlayer insulating film IL. In this polishing step, the metalfilm is removed from over the interlayer insulating film IL to form theplugs CP each made of the metal film in the respective contact holes.The plugs CP are made mainly of, e.g., W (tungsten). It is conceivablethat each of the plugs CP includes, e.g., a main conductor film made ofW (tungsten) and a barrier conductor film covering the side and bottomsurfaces of the main conductor film. However, in the drawings, theillustration of a multi-layer structure including the main conductorfilm and the barrier conductor film is omitted, and the plug CP is shownas a single conductor film. As the material of the barrier conductorfilm, e.g., TiN (titanium nitride) can be used.

Subsequently, over the interlayer insulating film IL, the wires M1 areformed. Each of the wires M1 is made of a multi-layer structureincluding a barrier conductor film (such as, e.g., a titanium nitridefilm, a tantalum film, or a tantalum nitride film) and a main conductorfilm (copper film) formed over the barrier conductor film. In thedrawing, for simpler illustration, the barrier conductor film and themain conductor film are integrally shown as each of the wires M1.

The wires M1 can be formed by, e.g., a so-called single damascenemethod. Specifically, by forming an interlayer insulating film havingwire trenches over the interlayer insulating film IL and embedding ametal film in the wire trenches, the wires M1 can be formed. However,the illustration of the interlayer insulating film located lateral tothe wires M1 is omitted herein.

By the process described above, the semiconductor device in the presentfirst embodiment is generally completed.

<Effects of Manufacturing Method of Semiconductor Device>

Next, a description will be given of the effects of the manufacturingmethod of the semiconductor device in the present first embodiment.

As described above about the effects of the semiconductor device in thepresent first embodiment, in the present first embodiment, to preventcharges from being trapped in the gate insulating film including theferroelectric film HK2, the paraelectric film HK1 is formed as theinterfacial layer (block layer) between the ferroelectric film HK2 andthe semiconductor substrate SB. This can prevent the electric fieldinduced in the ferroelectric film HK2 from causing dielectric breakdownin the interfacial layer. Therefore, it is possible to improve thereliability of the semiconductor device.

Also, in the present first embodiment, as described using FIG. 3, thecrystals GR2 in the ferroelectric film HK2 are formed larger than thecrystals GR1 in the paraelectric film HK1 to allow the residualpolarization in the ferroelectric film HK2 to be increased. This canreduce the operating voltage of the ferroelectric film and improve theinformation retention property of the ferroelectric memory. Therefore,it is possible to improve the performance of the semiconductor device.Since the paraelectric film HK1 is formed as the interfacial layer incontact with the lower surface of the ferroelectric film HK2, thecrystals GR2 can be formed larger than the crystals GR1.

Also, in the present first embodiment, in the second heat treatmentdescribed using FIGS. 12 and 13, heating is performed using themicrowave having the electric field which vibrates in the directionperpendicular to the main surface of the semiconductor substrate SB.This allows an orthorhombic crystal polarized in the perpendiculardirection to be grown in the ferroelectric film HK2. In other words, itis possible to prevent a crystal which is polarized in a direction otherthan the perpendicular direction from growing in the ferroelectric filmHK2. As a result, the plurality of crystals included in theferroelectric film HK2 are polarized in equal directions to allow theresidual polarization in the ferroelectric film HK2 to be increased.

By performing the second heat treatment using the microwave, it ispossible to achieve crystallization at a low temperature of not morethan 400° C. and allow an orthorhombic crystal to be easily formed inthe ferroelectric film HK2 formed thereby. Specifically, by increasingthe ratio of the orthorhombic crystals to all the crystals included inthe ferroelectric film HK2, it is possible to increase the residualpolarization in the ferroelectric film HK2.

By performing the second heat treatment with the metal film MF1 beingformed over the high-k film AM2 (see FIG. 11), it is possible toincrease the likelihood of formation of the orthorhombic crystals in theferroelectric film HK2.

As described above, by increasing the likelihood of formation of theorthorhombic crystals in the ferroelectric film HK2, it is possible toenhance the polarization performance of the ferroelectric film HK2.Briefly, even when the voltage applied to the control gate electrode CG1of the memory cell MC1 is low, the ferroelectric film HK2 can bepolarized to allow a reduction in the power consumption of theferroelectric memory. In addition, the increased residual polarizationallows an improvement in retention property. Therefore, it is possibleto improve the performance of the semiconductor device.

<Modification 1>

In the present first modification, a description will be given offormation of a thin insulating film between the paraelectric layer asthe interfacial layer and the main surface of the semiconductorsubstrate.

In a manufacturing process of a semiconductor device in the presentfirst modification, after the insulating film IFA is processed by theprocess described using FIG. 7, as shown in FIG. 21, an insulating filmIFB is formed over the main surface of the semiconductor substrate SB ofthe memory cell MC1 using, e.g., an oxidation method. Then, the stepsdescribed using FIGS. 8 to 13 are performed. Alternatively, after theinsulating film IFA is formed by the step described using FIG. 6, it mayalso be possible to perform the steps described using FIGS. 8 to 13 withthe insulating film IFA remaining in the memory cell region MR withoutperforming the step of removing the insulating film IFA described aboveusing FIG. 7. The insulating film IFB is made of, e.g., a silicon oxidefilm and the thickness thereof is, e.g., 1 to 2 nm.

Subsequently, by performing the same steps as those described usingFIGS. 14 to 20, the semiconductor device in the present firstmodification shown in FIG. 22 can be formed. Consequently, the memorycell MC1 in the semiconductor device in the present first modificationhas the insulating film IFB, the paraelectric film HK1, theferroelectric film HK2, and the metal film MF1 which are stacked in thisorder over the main surface of the semiconductor substrate SB betweenthe main surface of the semiconductor substrate SB and the control gateelectrode CG1.

In the present first modification, between the paraelectric film HK1 andthe main surface of the semiconductor substrate SB, the insulating filmIFB is formed as a portion of the interfacial layer (block) layer. Thiscan prevent charges from being trapped in the ferroelectric film HK2 andthe paraelectric film HK1 during the operation of the memory cell MC1.

Specifically, when a positive voltage is applied to the control gateelectrode CG1 to bring the memory cell MC1 into an erased state (statewhere the threshold voltage of the transistor is low), it is possible toprevent charges from being trapped in the ferroelectric film HK2 and theparaelectric film HK1 and increasing the threshold voltage of thetransistor. On the other hand, when a negative voltage is applied to thecontrol gate electrode CG1 to bring the memory cell MC1 into a writtenstate (state where the threshold voltage of the transistor is high), itis possible to prevent the charges trapped in the ferroelectric film HK2and the paraelectric film HK1 from being extracted therefrom andreducing the threshold voltage of the transistor. This can prevent thedeterioration of the retention property of the memory cell MC1. This canalso prevent the deterioration of the performance of the ferroelectricmemory which switches the memory cell MC1 between the written state andthe erased state by controlling the threshold voltage. In addition, itis possible to reduce the power consumption of the memory cell MC1.

<Modification 2>

In the present second modification, a description will be given of thecase where another metal film is further inserted between theinterfacial layer and the ferroelectric film.

In a manufacturing process of the semiconductor device in the presentsecond modification, after the steps described using FIGS. 5 to 10 areperformed, as shown in FIG. 23, a metal film MF2 is formed over theparaelectric film HK1 using, e.g., a CVD method or a sputtering method.The metal film MF2 is made of, e.g., a TiN (titanium nitride) film andhas a thickness of, e.g., 10 to 20 nm. Then, the steps descried usingFIGS. 11 to 13 are performed.

Subsequently, by performing the same steps as those described usingFIGS. 14 to 20, the semiconductor device in the present secondmodification shown in FIG. 24 can be formed. Consequently, the memorycell MC1 in the semiconductor device in the present second modificationhas the paraelectric film HK1, the metal film MF2, the ferroelectricfilm HK2, and the metal film MF1 which are stacked in this order overthe main surface of the semiconductor substrate SB between the mainsurface of the semiconductor substrate SB and the control gate electrodeCG1.

When the metal film MF2 is not formed, the threshold voltage of thetransistor included in the memory cell MC1 is determined directly by thepolarization of each of the crystal grains of the ferroelectric film HK2so that a local threshold variation is likely to occur. By contrast, inthe present second modification, the metal film MF2 in an electricallyfloating state functions as an electrode and equalizes the electricfield resulting from the polarization of the ferroelectric film HK2.This can prevent the threshold voltage of the transistor from varyingand thus improve the performance and reliability of the semiconductordevice.

In the case where the metal film is inserted between the interfaciallayer and the ferroelectric film, when the electrostatic capacitance ofthe interfacial layer is low, a problem arises in that the electricfield is less likely to be applied to the ferroelectric film to increasea voltage for causing polarization inversion. When the interfacial layeris made of a silicon oxide film or a silicon nitride film as describedusing FIG. 75, the electrostatic capacitance of the interfacial layer issmall so that a voltage for causing polarization inversion as describedabove, i.e., voltage applied to the control gate electrode CG1increases. Consequently, the power consumption of the ferroelectricmemory increases to degrade the performance of the semiconductor device.

By contrast, in the present second modification, the metal film MF2 isinserted between the paraelectric film HK1 as the interfacial layer andthe ferroelectric film HK2, and the interfacial layer is formed of theparaelectric film HK1 having a dielectric constant (relativepermittivity) higher than that of silicon nitride. This prevent asituation in which the electric field generated by the voltage appliedto the control gate electrode CG1 is less likely to be applied to theferroelectric film HK2. Consequently, even a low gate voltage cancontrol the polarization of the ferroelectric film HK2 and reduce thepower consumption of the ferroelectric memory. Therefore, it is possibleto improve the performance of the semiconductor device.

Second Embodiment

<Structure of Semiconductor Device>

The following will describe a structure of a semiconductor device in thepresent second embodiment. FIG. 25 is a plan view of the semiconductordevice in the present second embodiment. FIG. 26 is a perspective viewof the semiconductor device in the present second embodiment. FIGS. 27and 28 are cross-sectional views of the semiconductor device in thepresent second embodiment. Note that, in FIGS. 26 and 28, theillustration of wells is omitted. Also, in FIG. 28, the illustration ofsource and drain regions is omitted.

In FIG. 25, a plan view of a memory cell array is shown in the memorycell region 1A, a plan view of an n-type transistor QN included in alogic circuit in a logic circuit region or the like is shown in the nMISregion 1B, and a plan view of a p-type transistor QP included in thelogic circuit in the logic circuit region or the like is shown in a pMISregion 1C. As an example of the n-type transistor QN, an n-type MISFETis shown. As an example of the p-type transistor QP, a p-type MISFET isshown. The following may refer to the n-type MISFET as nMIS and refer tothe p-type MISFET as the pMIS.

Each of memory cells MC2 formed in the memory cell region 1A is formedin, e.g., the ferroelectric memory CC5 in FIG. 1. The n-type transistorQN in the nMIS region 1B and the p-type transistor QP in the pMIS region1C are formed in, e.g., the RAM CC2 and the CPU CC1 in FIG. 1 or thelike.

As shown in FIG. 25, in the memory cell region 1A, a plurality of finsFA extending in the X-direction are equidistantly arranged in aY-direction. The X-direction and the Y-direction are directions alongthe main surface of the semiconductor substrate SB. The X-direction isorthogonal to the Y-direction. For example, the fins FA are cuboidalprotruding portions (projecting potions) selectively protruding from themain surface of the semiconductor substrate SB and having wall-like(plate-like) shapes. The lower end portions of the fins FA aresurrounded by the isolation region EI covering the main surface of thesemiconductor substrate SB. Each of the fins FA is a portion of thesemiconductor substrate SB serving as the active region of thesemiconductor substrate SB. In plan view, the spaces between theadjacent fins FA are filled with the isolation region EI so that theisolation region EI surrounds the peripheries of the fins FA. Each ofthe fins FA is the active region for forming the memory cell MC2.

Over the plurality of fins FA, a plurality of control gate electrodesCG2 and a plurality of memory gate electrodes MG each extending in theY-direction are disposed. In the upper surfaces of the fins FA, drainregions MD closer to the control gate electrodes CG2 and source regionsMS closer to the memory gate electrodes MS are formed such that thecontrol gate electrodes CG2 and the memory gate electrodes MG areinterposed therebetween. Specifically, the one of the control gateelectrodes CG2 and the one of the memory gate electrodes MG which areadjacent to each other in the X-direction are located between the sourceregion MS and the drain region MD.

The drain regions MD and the source regions MS are n-type semiconductorregions. Each of the drain regions MD is formed between the two controlgate electrodes CG2 adjacent to each other in the X-direction, whileeach of the source regions MS is formed between the two memory gateelectrodes MG adjacent to each other in the X-direction. Each of thememory cells MC2 is a nonvolatile storage element having the controlgate electrode CG2, the memory gate electrode MG, the drain region MD,and the source region MS. In the following, the source region MS and thedrain region which are included in the memory cell MC2 may be referredto also as source and drain regions.

The two memory cells MC2 adjacent to each other in the X-direction sharethe drain region MD or the source region MS. The two memory cells MC2sharing the drain region MD are line-symmetric in the X-directionrelative to the drain region MD extending in the Y-direction. The twomemory cells MC2 sharing the source region MS are line-symmetric in theX-direction relative to the source region MS extending in theY-direction.

In each of the fins FA, the plurality of memory cells MC2 arranged inthe X-direction are formed. The respective drain regions MD of theindividual memory cells MC2 are electrically coupled to a source line SLmade of the wire M1 extending in the X-direction via plugs PG1 (plugs)formed in contact holes extending through an interlayer insulating film(not shown) formed over the memory cells MC2. On the other hand, therespective source regions MS of the plurality of memory cells MC2arranged in the Y-direction are electrically coupled to a bit line BLmade of the wire M1 extending in the Y-direction.

In the nMIS region 1B, a fin FB extending in, e.g., the X-direction isformed. The fin FB is a portion of the semiconductor substrate SB,similarly to the fins FA, and has a wall-like (plate-like) shapeprotruding over the main surface of the semiconductor substrate SB. Thefin FB is the active region of the semiconductor substrate SB. The lowerend portion of the fin FB is surrounded by the isolation region EIcovering the main surface of the semiconductor substrate SB. Over thefin FB, a gate electrode G1 is disposed to extend in the Y-directionand, over the upper surface of the fin FB, a drain region LD1 and asource region LS1 are formed such that the gate electrode G1 isinterposed therebetween. The drain region LD1 and the source region LS1are n-type semiconductor regions.

The n-type transistor QN has the gate electrode G1, the drain regionLD1, and the source region LS1. The gate electrode G1, the drain regionLD1, and the source region LS1 are electrically coupled to the wires M1via plugs PG2 formed in contact holes. The fin FB is the active regionfor forming the n-type transistor QN.

In the pMIS region 1C, a fin FC extending in the X-direction and thep-type transistor QP located thereover are formed. The layout of thep-type transistor QP including a gate electrode G2, a drain region LD2,and a source region LS2 is the same as that of, e.g., the n-typetransistor QN.

Each of the fins FA, FB, and FC is, e.g., a cuboidal protruding portionprotruding from the main surface of the semiconductor substrate SB in adirection perpendicular to the main surface. Each of the fins FA, FB,and FC need not necessarily have a cuboidal shape, but may also have arectangular shape having rounded corners in cross-sectional view in ashort-side direction. Also, as shown in FIG. 28, the respective sidesurfaces of the fins FA, FB, and FC may be perpendicular to the mainsurface of the semiconductor substrate SB or may have inclination anglesclose to 90 degrees. In short, the cross-sectional shape of each of thefins FA, FB, and FC is either a cuboid or a trapezoid. The respectiveside surfaces of the fins FA, FB, and FC are obliquely inclined relativeto the main surface of the semiconductor substrate SB.

As shown in FIG. 25, the direction in which each of the fins FA, FB, andFC extends in plan view is the long-side direction of each of the fins,while the direction orthogonal to the long-side direction is theshort-side direction of each of the fins. Thus, the length of each ofthe fins is larger than the width of the fin. Each of the fins FA, FB,and FC may have any shape as long as the fin is a protruding portionhaving a length, a width, and a height. For example, each of the finsFA, FB, and FC may also have a meandering layout in plan view.

FIGS. 26 to 28 show the memory cell region 1A, the nMIS region 1B, andthe pMIS region 1C which are arranged in this order in a left-to-rightdirection. In FIG. 26, the illustration of the isolation region EI aswell as the interlayer insulating film and the wires over each of theelements is omitted. Over the fins FA included in the semiconductorsubstrate SB in the memory cell region 1A, the memory cells MC2 areformed. Over the fin FB included in the semiconductor substrate SB inthe nMIS region 1B, the n-type transistor QN is formed. Over the fin FCincluded in the semiconductor substrate SB in the pMIS region 1C, thep-type transistor QP is formed.

FIG. 27 shows a cross section of the semiconductor elements along theline A-A in FIG. 25, a cross section of the semiconductor elements alongthe line B-B in FIG. 25, and a cross section of the semiconductorelements along the line C-C in FIG. 25 in this order in the left-rightdirection. FIG. 28 shows a cross section of the semiconductor elementalong the line D-D in FIG. 25, a cross section of the semiconductorelement along the line E-E in FIG. 25, and a cross section of thesemiconductor element along the line F-F in FIG. 25 in this order in theleft-right direction. Over each of the fins, the plurality of elementsare formed but, in FIGS. 26 and 27, only one element is shown over eachof the fins.

As shown in FIG. 26, the control gate electrode CG2 and the memory gateelectrode MG extend in the Y-direction so as to mount over the fin FA,the gate electrode G1 extends in the Y-direction so as to mount over thefin FB, and the gate electrode G2 extends in the Y-direction so as tomount over the fin FC. The respective upper surfaces of the control gateelectrode CG2 and the memory gate electrode MG are covered with silicidelayers S2. The silicide layers S2 are made of, e.g., NiSi (nickelsilicide). Note that the silicide layers S2 may also contain Pt(platinum).

As shown in FIGS. 26 to 28, the side and upper surfaces of the fin FA inwhich the diffusion regions D1 included in the source and drain regionsin the memory cell region 1A are formed are covered with the silicidelayers S1. The silicide layers S1 are made of, e.g., NiSi (nickelsilicide). On the other hand, the side and upper surfaces of the fin FBin which the diffusion regions D2 included in the source and drainregions in the nMIS region 1B are formed are covered with epitaxiallayers (semiconductor layers) EP1. Likewise, the side and upper surfacesof the fin FC in which diffusion regions D3 included in the source anddrain regions in the pMIS region 1C are formed are covered withepitaxial layers (semiconductor layers) EP2.

The silicide layers S1 and the epitaxial layers EP1 and EP2 are eachformed over the isolation region EI. The silicide layers S1 are eachmade of a layer extending along the upper and side surfaces of the finFA.

On the other hand, each of the epitaxial layers EP1 and EP2 formed by anepitaxial growth method has a rhomboidal shape in a cross section (seeFIG. 28) along the Y-direction. Specifically, the side surface of eachof the epitaxial layers EP1 in the nMIS region 1B which is not incontact with the fin FB has a lower side surface and an upper sidesurface. The lower side surface is inclined so as to go away from thefin FB in a direction along the main surface of the semiconductorsubstrate SB as the distance from the isolation region EI increasesupward. The upper side surface is inclined so as to come closer to thefin FB in the direction along the main surface of the semiconductorsubstrate SB as the distance from the isolation region EI increasesupward. The upper end of the lower side surface is coupled to the lowerend of the upper side surface.

In other words, in the Y-direction, the width of the epitaxial layer EP1between the left terminal portion thereof and the right terminal portionthereof is larger at the middle portion between the upper and lower endsof the epitaxial layer EP1 than at the upper and lower ends thereof.Note that each of the epitaxial layers EP2 in the pMIS region 1C alsohas the same shape as that of each of the epitaxial layers EP1 in thenMIS region 1B. The epitaxial layers EP1 in the nMIS region 1B are madeof, e.g., SiP (silicon phosphide) or SiC (silicon carbide). Theepitaxial layers EP2 in the pMIS region 1C are made of SiGe (silicongermanium).

The epitaxial layers EP1 in the nMIS region 1B are semiconductor layersin which an n-type impurity (e.g., P (phosphorus) or As (arsenic)) isintroduced and included in the diffusion regions D2 of the n-typetransistor QN. The epitaxial layers EP2 in the pMIS region 1C aresemiconductor layers in which a p-type impurity (e.g., B (boron)) isintroduced and included in the diffusion regions D3 of the p-typetransistor QP.

As shown in FIGS. 26 and 27, each of the lower portions of therespective side surfaces of the fins FA, FB, and FC is surrounded by theisolation region EI formed over the main surface of the semiconductorsubstrate SB. In short, the individual fins are isolated from each otherby the isolation region EI. In each of the fins FA, the p-type well PW1as the p-type semiconductor region is formed to extend from the uppersurface of the fin FA to the lower portion thereof. Likewise, in the finFB, the p-type well PW2 as the p-type semiconductor region is formed toextend from the upper surface of the fin FB to the lower portionthereof. In the fin FC, an n-type well NW as an n-type semiconductorregion is formed to extend from the upper surface of the fin FC to thelower portion thereof.

Over the upper and side surfaces of each of the fins FA, the controlgate electrode CG2 is formed via a gate insulating film GF. In theregion adjacent to the control gate electrode CG2 in the long-sidedirection (X-direction) of the fin FA, the memory gate electrode MG isformed via a multi-layer film including the paraelectric film HK1, theferroelectric film HK2, and the metal film MF1. Between the control gateelectrode CG2 and the memory gate electrode MG, the multi-layer film isinterposed. The control gate electrode CG2 and the memory gate electrodeMG are electrically isolated from each other by the paraelectric filmHK1 as the insulating film and the ferroelectric film HK2 as theinsulating film. Between the memory gate electrode MG and the uppersurface of the fin FA, the multi-layer film including the paraelectricfilm HK1, the ferroelectric film HK2, and the metal film MF1 which arestacked in this order over the fin FA is interposed. The multi-layerfilm is formed continuously so as to cover the side and bottom surfacesof the memory gate electrode MG. Consequently, each of the paraelectricfilm HK1, the ferroelectric film HK2, and the metal film MF1 which areincluded in the multi-layer film has an L-shaped cross-sectional shape.

The gate insulating film GF is a thermal oxidation film (silicon oxidefilm) formed by thermally oxidizing the upper and side surfaces of thefin FA as the protruding portion of the semiconductor substrate SB madeof silicon. The gate insulating film GF has a thickness of, e.g., 2 nm.The paraelectric film HK1, the ferroelectric film HK2, and the metalfilm MF1 are made of the same materials as in the foregoing firstembodiment and have the same thicknesses as in the foregoing firstembodiment.

As shown in the memory cell region 1A, in the short-side direction(Y-direction) of the fin FA, the control gate electrode CG2 extendsalong the upper and side surfaces of the fin FA and the upper surface ofthe isolation region EI via the gate insulating film GE. Likewise, inthe short-side direction of the fin FA, the memory gate electrode MGextends along the upper and side surfaces of the fin FA and the uppersurface of the isolation region EI via the multi-layer film. Over therespective main surfaces of the control gate electrode CG2 and thememory gate electrode MG, the silicide layers S2 are formed.

The side surfaces of a pattern including the control gate electrode CG2,the memory gate electrode MG, the gate insulating film GF, theparaelectric film HK1, the ferroelectric film HK2, the metal film MF1,and the silicide layers S2 are covered with the sidewall spacers SW.Each of the sidewall spacers SW is made of a multi-layer structureincluding, e.g., a silicon nitride film and a silicon oxide film. Thesilicide layers S1 cover the respective surfaces of the patternincluding the control gate electrode CG2 and the fins FA exposed fromthe foregoing sidewall spacers SW.

As shown in FIG. 27, the pair of source and drain regions are formed inthe upper surface of the fin FA such that the upper surface of the finFA located immediately below the pattern including the control gateelectrode CG2 is interposed therebetween. Each of the source region andthe drain region includes the extension region EX1 as an n⁻-typesemiconductor region and the diffusion region D1 as an n⁺-typesemiconductor region. The diffusion region D1 has an impurityconcentration higher than that of the extension region EX1 and is formeddeeper than the extension region EX1. In each of the source region andthe drain region, the extension region EX1 and the diffusion region D1are in contact with each other. The extension region EX1 is locatedcloser to the upper surface of the fin FA immediately below theforegoing pattern, i.e., closer to the channel region than the diffusionregion D1.

By thus forming the source and drain regions each having a structureincluding the lower-impurity-concentration extension region EX1 and thehigher-impurity-concentration diffusion region D1, i.e., an LDDstructure, it is possible to improve the short channel property of thetransistor having the source and drain regions. The source regioncorresponds to the source region MS shown in FIG. 25. The drain regioncorresponds to the drain region MD shown in FIG. 25.

Over the fin FA and the isolation region EI, an interlayer insulatingfilm IL1 made of, e.g., a silicon oxide film is formed. Over therespective upper surfaces of the interlayer insulating film IL1, thecontrol gate electrode CG2, the memory gate electrode MG, the sidewallspacers SW, and the silicide layers S2, an interlayer insulating filmIL2 made of, e.g., a silicon oxide film is formed. The upper surface ofthe interlayer insulating film IL1 is planarized to be generally flushwith the respective upper surfaces of the paraelectric film HK1, theferroelectric film HK2, the metal film MF1, the sidewall spacers SW, andthe silicide layers S2.

Over the interlayer insulating film IL2, the plurality of wires M1 areformed. The wires M1 are electrically coupled to the foregoing sourceregion and the foregoing drain region of the memory cell MC2 via theplugs PG1 provided in contact holes CH extending through the interlayerinsulating films IL2 and IL1. As a result, the bottom surfaces of theplugs PG1 are in direct contact with the upper surfaces of the silicidelayers S1 so that the plugs PG1 are electrically coupled to the sourceand drain regions via the silicide layers S1. The silicide layers S1have the function of reducing the coupling resistances between the plugsPG1 as the coupling portions made of a metal film mainly containing,e.g., tungsten (W) and the source and drain regions in the fin FA madeof a semiconductor.

A description will be given herein of the case where each of the contactholes CH and the plugs PG1 and PG2 has a round shape in plan view.Alternatively, each of the contact holes CH and the plugs PG1 and PG2may also have a rectangular shape in plan view. Each of the contactholes CH and the plugs PG1 and PG2 may also have a width larger thanthat of each of the silicide layers S1 and the epitaxial layers EP1 andEP2 in the short-side direction (Y-direction) of each of the fins.

By covering the fin FA in which the source and drain regions are formedwith the silicide layer S1, it is possible to reduce the resistances ofthe source and drain regions and thus improve the performance of thememory cell MC2.

The memory cell MC2 includes the control gate electrode CG2, theparaelectric film HK1, the ferroelectric film HK2, the memory gateelectrode MG, the drain region, and the source region. The control gateelectrode CG2 and the source and drain regions are included in a controltransistor. The paraelectric film HK1, the ferroelectric film HK2, thememory gate electrode MG, and the source and drain regions are includedin a memory transistor. The memory cell MC2 includes the controltransistor and the memory transistor. In short, the control transistorand the memory transistor share the source and drain regions. Thedistance between the drain region and the source region of the controlgate electrode CG2 and the memory gate electrode MG in the gate lengthdirection (X-direction) corresponds to the channel length of the memorycell MC2.

In the nMIS region 1B, over the main and side surfaces of the fin FB,the gate electrode G1 is formed via an insulating film HK functioning asa gate insulating film. Note that the insulating film HK continuouslycovers the bottom and side surfaces of the gate electrode G1. Theinsulating film HK is an insulating material film having a dielectricconstant (relative permittivity) higher than that of silicon nitride,i.e., a so-called high-k film (high-dielectric-constant film). The gateelectrode G1 includes a metal film MF3 covering the top surface of theinsulating film HK and a metal film MF4 formed over the insulating filmHK via the metal film MF3. The metal film MF3 is made of, e.g., TiAl(titanium aluminum). The metal film MF4 is made of, e.g., Al (aluminum).Note that, between the fin FB and the insulating film HK, a siliconoxide film may also be formed as a portion of the gate insulating film,but the silicon oxide film is not shown herein.

In the short-side direction (Y-direction) of the fin FB, the gateelectrode G1 continuously extends along the upper and side surfaces ofthe fin FB and the upper surface of the isolation region EI via theinsulating film HK. The side surfaces of the gate electrode G1 arecovered with the sidewall spacers SW.

Each of the source region and the drain region which are provided inareas lateral to the gate electrode G1 such that the gate electrode G1is interposed therebetween in the X-direction includes the extensionregion EX2 as an n⁻-type semiconductor region and the diffusion regionD2 as an n⁺-type semiconductor region, i.e., has an LDD structure. Thediffusion region D2 is formed extensively in the fin FB and theepitaxial layer EP1 formed lateral to the gate electrode G1 via thesidewall spacer SW. The extension region EX2 is formed in the fin FB.The source region corresponds to the source region LS1 shown in FIG. 25,while the drain region corresponds to the drain region LD1 shown in FIG.25.

In the nMIS region 1B, over the fin FB and the isolation region EI, theinterlayer insulating films IL1 and IL2 are formed in this order in thesame manner as in the memory cell region 1A. However, between theinterlayer insulating film IL1 and the interlayer insulating film IL2,an insulating film IF9 is formed so as to cover the upper surface of thegate electrode G1. The upper surface of the interlayer insulating filmIL1 is planarized together with the respective upper surfaces of thegate electrode G1, the insulating film HK, and the sidewall spacers SW.The interlayer insulating film IL1 covers the upper surfaces of theepitaxial layers EP1 so that the upper surfaces of the epitaxial layerEP1 are in direct contact with the interlayer insulating film IL1.Consequently, between the upper surfaces of the epitaxial layers EP1 andthe interlayer insulating film IL1, no silicide layer is interposed.

Over the interlayer insulating film IL2, the wires M1 are formed andelectrically coupled to the source region and the drain region via theplugs PG2 provided in the contact holes CH extending through theinterlayer insulating films IL2 and IL1. Between the plugs PG2 and theepitaxial layers EP1, silicide layers S3 are interposed. The silicidelayers S3 are made of, e.g., TiSi₂ (titanium silicide).

The silicide layers S3 are formed immediately below the plugs PG2, i.e.,only at the bottom portions of the contact holes CH. The upper surfacesof the epitaxial layers EP1 located in the areas lateral to the plugsPG2 are exposed from the silicide layers S3. The silicide layers S3 havethe function of reducing the coupling resistances between the plugs PG2as the coupling portions made of a metal film mainly containing, e.g.,tungsten (W) and the source and drain regions in the epitaxial layersEP1 made of the semiconductor.

The n-type transistor QN includes the gate electrode G1, the drainregion, and the source region. The distance between the drain region andthe source region of the gate electrode G1 in the gate length direction(X-direction) corresponds to the channel length of the n-type transistorQN.

In the pMIS region 1C, over the main and side surfaces of the fin FC,the gate electrode G2 is formed via the insulating film HK functioningas a gate insulating film. Note that the insulating film HK continuouslycovers the bottom and side surfaces of the gate electrode G2. Theinsulating film HK is an insulating material film having a dielectricconstant (relative permittivity) higher than that of silicon nitride,i.e., a so-called high-k film (high-dielectric-constant film). The gateelectrode G2 includes a metal film MF5 covering the top surface of theinsulating film HK and a metal film MF6 formed over the insulating filmHK via the metal film MF5. The metal film MF5 is made of, e.g., TiAl(titanium aluminum), while the metal film MF6 is made of, e.g., Al(aluminum). Note that, between the fin FC and the insulating film HK, asilicon oxide film may also be formed as a portion of the gateinsulating film, but the silicon oxide film is not shown herein.

In the short-side direction (Y-direction) of the fin FC, the gateelectrode G2 continuously extends along the upper and side surfaces ofthe fin FC and the upper surface of the isolation region EI via theinsulating film HK. The side surfaces of the gate electrode G2 arecovered with the sidewall spacers SW.

Each of the source region and the drain region which are provided inareas lateral to the gate electrode G2 such that the gate electrode G2is interposed therebetween in the X-direction includes an extensionregion EX3 as a p⁻-type semiconductor region and the diffusion region D3as a p⁺-type semiconductor region, i.e., has an LDD structure. Thediffusion region D3 is formed extensively in the fin FC and theepitaxial layer EP2 formed lateral to the gate electrode G2 via thesidewall spacer SW. The extension region EX3 is formed in the fin FC.The source region corresponds to the source region LS2 shown in FIG. 25,while the drain region corresponds to the drain region LD2 shown in FIG.25.

In the pMIS region 1C, over the fin FC and the isolation region EI, theinterlayer insulating film IL1, the insulating film IF9, and theinterlayer insulating film IL2 are formed in this order in the samemanner as in the nMIS region 1B. The upper surface of the interlayerinsulating film IL1 is planarized together with the respective uppersurfaces of the gate electrode G2, the insulating film HK, and thesidewall spacers SW. The interlayer insulating film IL1 covers the uppersurfaces of the epitaxial layers EP2 so that the upper surfaces of theepitaxial layers EP2 are in direct contact with the interlayerinsulating film IL1. Consequently, between the upper surfaces of theepitaxial layers EP2 and the interlayer insulating film IL1, no silicidelayer is interposed.

Over the interlayer insulating film IL2, the wires M1 are formed andelectrically coupled to the source region and the drain region via theplugs PG2 provided in the contact holes CH extending through theinterlayer insulating films IL2 and IL1. Between the plugs PG2 and theepitaxial layers EP2, the silicide layers S3 are interposed. Thesilicide layers S3 are made of, e.g., TiSi₂ (titanium silicide).

The silicide layer S3 are formed immediately below the plugs PG2, i.e.,only at the bottom portions of the contact holes CH. The upper surfacesof the epitaxial layers EP2 located in the areas lateral to the plugsPG2 are exposed from the silicide layers S3. The silicide layers S3 havethe function of reducing the coupling resistances between the plugs PG2as the coupling portions made of the metal film mainly containing, e.g.,tungsten (W) and the source and drain regions in the epitaxial layersEP2 made of a semiconductor.

The p-type transistor QP includes the gate electrode G2, the drainregion, and the source region. The distance between the drain region andthe source region of the gate electrode G2 in the gate length direction(X-direction) corresponds to the channel length of the p-type transistorQP.

<Operations in Nonvolatile Memory>

Next, a description will be given of an example of operations in thenonvolatile memory with reference to FIG. 29.

FIG. 29 is a table showing an example of conditions under which voltagesare applied to the individual portions of a selected memory cell during“Write”, “Erase”, and “Read” operations. In the table of FIG. 29, thevoltage Vd applied to the drain region of the memory cell (selectedmemory cell) MC2 shown in FIG. 28, a voltage Vcg applied to the controlgate electrode CG2 thereof, a voltage Vmg applied to the memory gateelectrode MG thereof, the voltage Vs applied to the source regionthereof, and the voltage Vb applied to the p-type well PW1 thereofduring each of the “Write”, “Erase”, and “Read” operations are shown.Note that what is shown in the table of FIG. 29 is a preferred exampleof the conditions for voltage application. The conditions for voltageapplication are not limited thereto, and can variously be changed asnecessary.

In the present second embodiment, bringing the memory cell MC2 into thestate where the ferroelectric film HK2 is upwardly polarized and thethreshold voltage of the transistor included in the memory cell MC2 isrelatively high is defined as the “Write” operation. On the other hand,bringing the memory cell MC2 into the state where the ferroelectric filmHK2 is downwardly polarized and the threshold voltage of the transistorincluded in the memory cell MC2 is relatively low is defined as the“Erase” operation”.

In the present second embodiment, the “Write” operation to the memorycell MC2 is performed by applying a negative voltage to the memory gateelectrode MG thereof. Specifically, such voltages as shown in, e.g., the“Write” row in FIG. 29 are applied to the individual portions of theselected memory cell to which the “Write” operation is performed. Thus,the ferroelectric film HK2 of the selected memory cell is upwardlypolarized to effect the “Write” operation. This increases the thresholdvoltage of the transistor included in the memory cell MC2. As a result,the memory cell MC2 is brought into the written state.

In the present second embodiment, the “Erase” operation to the memorycell MC2 is performed by applying a positive voltage to the memory gateelectrode MG thereof. Specifically, such voltages as shown in, e.g., the“Erase” row in FIG. 29 are applied to the individual portions of theselected memory cell to which the “Erase” operation is performed. Thus,the ferroelectric film HK2 of the selected memory cell is downwardlypolarized to effect the “Erase” operation. This reduces the thresholdvoltage of the transistor included in the memory cell MC2. As a result,the memory cell MC2 is brought into the erased state.

When the “Read” operation is performed, such voltages as shown in, e.g.,the “Read” row in FIG. 29 are applied to the individual portions of theselected memory cell to which the “Read” operation is performed. Bysetting the voltage Vmg to be applied to the memory gate electrode MGduring the “Read” operation to a value between the threshold voltage ofthe foregoing transistor in the written state and the threshold voltageof the foregoing transistor in the erased state, the written state orthe erased state can be determined.

<Effects of Semiconductor Device>

From the semiconductor device in the present second embodiment, the sameeffects as obtained from the semiconductor device in the foregoing firstembodiment can be obtained.

Specifically, by forming the paraelectric film HK1 as the interfaciallayer, it is possible to prevent the electric field induced in theferroelectric film HK2 from causing dielectric breakdown of theinterfacial layer. As a result, it is possible to improve thereliability of the semiconductor device. In addition, as described usingFIG. 3, the crystals GR2 included in the ferroelectric film HK2 areformed larger than the crystals GR1 included in the paraelectric filmHK1 to allow residual polarization in the ferroelectric film HK2 to beincreased. This can reduce the operating voltage of the ferroelectricmemory and improve the information retention property of theferroelectric memory. Therefore, it is possible to improve theperformance of the semiconductor device.

Under the ferroelectric film HK2, the paraelectric film HK1 is formedherein to come in contact with the lower surface of the ferroelectricfilm HK2 so that crystal nuclei are less likely to be formed over theupper surface of the paraelectric film HK1 as the interfacial layer.This can reduce the number of the crystals GR2 included in theferroelectric film HK2 and allow each of the crystals GR2 to be grownlarge.

<Manufacturing Process of Semiconductor Device>

Using FIGS. 30 to 74, the following will describe a method ofmanufacturing the semiconductor device in the present second embodiment.FIGS. 30, 32, 34, 36, 39, 41, and 43 to 74 are cross-sectional views ofthe semiconductor device in the present second embodiment during theformation process thereof. FIGS. 31, 33, 35, 37, 38, 40, and 42 areperspective views of the semiconductor device in the present secondembodiment during the formation process thereof. FIGS. 32, 34, 36, 39,41, and 43 are views showing cross sections at the same position inFIGS. 31, 33, 35, 38, 40, and 42 along the Y-direction. In the foregoingperspective views, the illustration of the wells is omitted.

FIGS. 30 to 44 show the memory cell region 1A and the logic circuitregion 1D which are arranged in this order in the left-to-rightdirection. FIGS. 45 to 74 show the memory cell region 1A, the nMISregion 1B, and the pMIS region 1C which are arranged in this order inthe left-to-right direction. The nMIS region 1B and the pMIS region 1Care included in the logic circuit region 1D.

First, as shown in FIG. 30, the semiconductor substrate SB is providedherein and, over the main surface of the semiconductor substrate SB, aninsulating film IF1, an insulating film IF2, and a semiconductor filmSI1 are formed in this order. The semiconductor substrate SB is made ofp-type monocrystalline silicon having a specific resistance of, e.g.,about 1 to 10 Ωcm or the like. The insulating film IF1 is made of, e.g.,a silicon oxide film and can be formed using, e.g., an oxidation methodor a CVD method. The insulating film IF1 has a thickness of about 2 to10 nm. The insulating film IF2 is made of, e.g., a silicon nitride filmand has a thickness of about 20 to 100 nm. The insulating film IF2 isformed by, e.g., a CVD method. The semiconductor film SI1 is made of,e.g., a silicon film and formed by, e.g., a CVD method. Thesemiconductor film SI1 has a thickness of, e.g., 20 to 200 nm.

Next, as shown in FIGS. 31 and 32, using a photolithographic techniqueand an etching method, the semiconductor film SI1 located in the memorycell region 1A and the logic circuit region 1D is processed. As aresult, over the insulating film IF2, a plurality of patterns made ofthe plurality of semiconductor films SI1 extending in the X-directionare formed to be arranged in the Y-direction. FIG. 32 is across-sectional view including the patterns made of the plurality ofsemiconductor films SI1 shown in FIG. 31.

The width of each of the patterns in the Y-direction in the memory cellregion 1A is larger than the width of each of the patterns in theY-direction in the logic circuit region 1D. In the Y-direction, theintervals between the patterns arranged in the memory cell region 1A arelarger than the intervals between the patterns arranged in the logiccircuit region 1D. Since the fins are formed in the areas close to thesemiconductor film SI1 in the Y-direction in the subsequent step, theintervals between the adjacent fins can be adjusted by changing thewidths of the patterns and the intervals therebetween.

Next, as shown in FIGS. 33 and 34, hard masks HN1 are formed to coverthe respective side surfaces of the plurality of semiconductor filmsSI1. For example, over the semiconductor substrate SB, a silicon oxidefilm having a thickness of 10 to 40 nm is formed herein using a CVDmethod and then dry-etched by anisotropic etching. By thus exposing therespective upper surfaces of the insulating film IF2 and thesemiconductor films SI1, the hard masks HM1 made of the silicon oxidefilm remaining over the side surfaces of the semiconductor films SI1 areformed. The hard masks HM1 do not completely fill up the spaces betweenthe adjacent semiconductor films SI1. As shown in FIG. 33, the hardmasks HM1 are each formed in an annular shape so as to surround therespective semiconductor films SI1.

Next, as shown in FIGS. 35 and 36, using a wet etching method, thesemiconductor films SI1 are removed. Subsequently, a photoresist filmPR1 is formed to cover the hard masks HM1 in the memory cell region 1Aand expose the hard masks HM1 in the logic region 1D. Subsequently, wetetching is performed to partly remove the top surfaces of the hard masksHM1. Thus, the width of each of the hard masks HM1 in the logic circuitregion 1D is reduced. Note that the width mentioned in the presentinvention refers to a length of a pattern or the like in a directionalong the main surface of the semiconductor substrate SB.

The hard masks HM1 are used to form the fins immediately therebelow.Accordingly, by producing the difference between the width of each ofthe hard masks HM1 in the memory cell region 1A and the width of each ofthe hard masks HM1 in the logic circuit region 1D as described above, itis possible to produce the difference between the width of the finformed in the memory region 1A and the width of the fin formed in thelogic circuit region 1D.

Next, as shown in FIG. 37, the photoresist film PR1 is removed, and thena photoresist film PR2 is formed to partly cover each of the hard masksHM1 in the memory cell region 1A and each of the hard masks HM1 in thelogic circuit region 1D. The photoresist film PR2 is a resist patterncovering the portions of the hard masks HM1 extending in the X-directionand exposing the ends of the portions thereof extending in theX-direction and the portions of the hard masks HM1 extending in theY-direction. As a result, the both ends of the hard masks HM1 in theX-direction are exposed from the photoresist film PR2.

Next, as shown in FIGS. 38 and 39, etching is performed using thephotoresist film PR2 as a mask to partly remove each of the hard masksHM1 and then remove the photoresist film PR2. As a result, only theportions of the hard masks HM1 extending in the X-direction are left. Inother words, over the insulating film IF2, the plurality of hard masksHM1 in the patterns extending in the X-direction are disposed to bearranged in the Y-direction.

Next, as shown in FIGS. 40 and 41, using the hard masks HM1 as a mask,anisotropic dry etching is performed on the insulating films IF2 and IF1and the semiconductor substrate SB. Thus, immediately below the hardmasks HM1, patterns as the portions of the semiconductor substrate SBwhich are processed into plate-like shapes (wall-like shapes), i.e., thefins FA, FB, and FC are formed. By lowering the level of the mainsurface of the semiconductor substrate SB located in the areas exposedfrom the hard masks HM1 by 100 to 250 nm, the fins FA, FB, and FC eachhaving a height of 100 to 250 nm from the main surface of thesemiconductor substrate SB can be formed.

Next, as shown in FIGS. 42 and 43, over the semiconductor substrate SB,an insulating film made of a silicon oxide film or the like is depositedsuch that the fins FA, FB, and FC and the insulating films IF1 and IF2are completely buried therein. Subsequently, a polishing process using aCMP method is performed on the insulating film to expose the uppersurface of the insulating film IF2. Thus, the isolation region EI madeof the insulating film is formed. By the CMP step, the hard masks HM1are removed. Note that the hard masks HM1 may also be removed before theinsulating film forming the isolation region EI is formed.

Next, as shown in FIG. 44, the insulating films IF1 and IF2 are removed.Subsequently, an etching process is performed on the upper surface ofthe isolation region EI to retreat (lower) the upper surface of theisolation region EI in a height direction. This partly exposes each ofthe side surfaces of the fins FA, FB, and FC and exposes the entireupper surfaces of the fins FA, FB, and FC.

Subsequently, using an ion implantation method, an impurity isintroduced into the main surface of the semiconductor substrate SB toform the p-type well PW1 in the fin FA in the memory cell region 1A,form the p-type well PW2 in the fin FB in the logic circuit region 1D,and form the n-type well NW in the fin FC in the logic circuit region1D. The p-type wells PW1 and PW2 are formed by implanting a p-typeimpurity (e.g., B (boron)). The n-type well NW is formed by implantingan n-type impurity (e.g., P (phosphorus) or As (arsenic)). The wells areformed to extend into the entire fins and into the portions of thesemiconductor substrate SB located under the fins.

Next, as shown in FIG. 45, an insulating film IF3 is formed to cover therespective upper and side surfaces of the fins FA, FB, and FC. Theinsulating film IF3 can be formed by, e.g., a thermal oxidation methodand made of a silicon oxide film having a thickness of, e.g., about 2nm. Subsequently, over the insulating film IF3, a semiconductor film SI2having a thickness of not less than the height of each of the fins FA,FB, and FC is deposited by a CVD method or the like. Then, byplanarizing the upper surface of the semiconductor film SI2 by a CMPmethod or the like, the semiconductor film SI2 having a planarized uppersurface is formed. Then, over the semiconductor film SI2, using, e.g., aCVD method, an insulating film IF4 is formed. The semiconductor film SI2is made of, e.g., a polysilicon film (silicon film), while theinsulating film IF4 is made of, e.g., a silicon nitride film. Even afterthe polishing step is performed on the semiconductor film SI2 using theCMP method as described above, the semiconductor film SI2 remains overthe upper surface of each of the fins FA, FC, and FC.

Next, as shown in FIG. 46, a photoresist film (not shown) is formed tocover the upper surface of a portion of the fin FA in the memory cellregion 1A as well as the nMIS region 1B and the pMIS region 1C. Thephotoresist film includes a resist pattern extending in the Y-directionwhich is formed to cover respective portions of the plurality of fins FAarranged in the Y-direction (depth direction in the drawing). In thearea located lateral to the resist pattern, the upper surface of the finFA is exposed from the photoresist film.

Subsequently, using the photoresist film as a mask, etching is performedto partly remove each of the insulating film IF4 and the semiconductorfilm SI2 in the memory cell region 1A to thus expose the upper surfaceof the isolation region EI and the top surface of the insulating filmIF3 in the memory cell region 1A. As a result, each of the upper andside surfaces of the fin FA is partly exposed from the insulating filmIF4 and the semiconductor film SI2. Thus, over the fin FA, the controlgate electrode CG2 made of the semiconductor film SI2 is formed. Inaddition, the gate insulating film GF made of the insulating film IF3located between the control gate electrode CG2 and the fin FA is alsoformed.

Note that a description will be given herein of the case where theinsulating film IF3 covering the top surface of the fin FA exposed fromthe control gate electrode CG2 is removed by the foregoing etching and acleaning step subsequently performed to expose the top surface of thefin FA. However, the upper and side surfaces of the fin FA may alsoremain covered with the insulating film IF3.

Next, as shown in FIG. 47, over the semiconductor substrate SB, theparaelectric film HK1, the ferroelectric film HK2, and the metal filmMF1 are formed by being deposited in this order. The steps of formingthe paraelectric film HK1, the ferroelectric film HK2, and the metalfilm MF1 are the same as the steps described using FIGS. 8 to 13.

A multi-layer film including the paraelectric film HK1, theferroelectric film HK2, and the metal film MF1 over the semiconductorsubstrate SB covers the upper surface of the isolation region EI and theupper and side surfaces of the fin FA. The multi-layer film also coversthe upper and side surfaces of a multi-layer pattern including thecontrol gate electrode CG2 and the insulating film IF4.

Next, as shown in FIG. 48, over the semiconductor substrate SB, using,e.g., a CVD method, a semiconductor film S13 is formed. Thesemiconductor film S13 is made of, e.g., a polysilicon film and has athickness larger than the height of the multi-layer body including thecontrol gate electrode CG2 and the insulating film IF4. Subsequently,the upper surface of the semiconductor film S13 is polished by a CMPmethod to expose the upper surface of a multi-layer film including theferroelectric film HK2 and the metal film MF1 over the insulating filmIF4.

Next, as shown in FIG. 49, an etch-back step is performed to retreat theupper surface of the semiconductor film S13. As a result, the positionof the upper surface of the semiconductor film S13 is at a heightsubstantially equal to that of, e.g., the position of the upper surfaceof the control gate electrode CG.

Next, as shown in FIG. 50, over the semiconductor substrate SB, using,e.g., a CVD method, an insulating film IF5 is formed. The insulatingfilm IF5 is made of, e.g., a silicon nitride film and covers the sideand upper surfaces of the insulating film IF4 and the upper surface ofthe semiconductor film S13 via the foregoing multi-layer film.

Next, as shown in FIG. 51, dry etching is performed to partly remove theinsulating film IF5 and thus partly expose the upper surface of theforegoing multi-layer film and the upper surface of the semiconductorfilm S13. As a result, the insulating film IF5 remains in asidewall-like shape over each of the side surfaces of the insulatingfilm IF4 via the foregoing multi-layer film. Subsequently, etching isperformed using the insulating film IF5 as a mask to process thesemiconductor film S13. As a result, the semiconductor film S13 remainsin the areas close to the both side surfaces of the control gateelectrode CG2, while the upper surface of the fin FA is exposed from thesemiconductor film S13 in the area other than the areas close to theboth side surfaces of the control gate electrode CG2.

The semiconductor film S13 close to one of the side surfaces of thecontrol gate electrode CG2 in the gate length direction (X-direction)via the foregoing multi-layer film forms the memory gate electrode MG.The memory gate electrode MG extends in the Y-direction in parallel withthe control gate electrode CG2 so as to mount over the plurality of finsFA.

Next, as shown in FIG. 52, a resist pattern (not shown) is formed tocover the memory gate electrode MG and the insulating film IF5 locatedimmediately thereabove. Then, using the resist pattern as a mask,etching is performed to remove the insulating film IF5 and thesemiconductor film S13 which are exposed from the resist pattern. As aresult, over one of the side surfaces of the control gate electrode CG2in the gate length direction, the memory gate electrode MG remains viathe foregoing multi-layer film, while the other side surface of thecontrol gate electrode CG2 is exposed from the semiconductor film S13.

Subsequently, etching is performed to remove the foregoing multi-layerfilm uncovered with the insulating film IF5 and the memory gateelectrode MG. This exposes the upper surface of the insulating film IF4,the upper surface of the fin FA, the side surfaces of the fin FA, andthe upper surface of the isolation region EI. This also exposes the sidesurface of the insulating film IF4 and the side surface of the controlgate electrode CG2 which are uncovered with the memory gate electrodeMG.

Next, as shown in FIG. 53, a photoresist film (not shown) is formed tocover the memory cell region 1A and the upper surface of a portion ofeach of the fins FB and FC in the nMIS region 1B and the pMIS region 1C.The photoresist film includes a resist pattern formed to partly covereach of the plurality of fins FB arranged in the Y-direction (depthdirection in the drawing) and extend in the Y-direction and a resistpattern formed to partly cover each of the plurality of fins FC arrangedin the Y-direction and extend in the Y-direction. In the areas locatedlateral to the resist pattern, the respective upper surfaces of the finsFB and FC are exposed from the photoresist film.

Subsequently, using the photoresist film as a mask, etching is performedto partly remove each of the insulating film IF4 and the semiconductorfilm SI2 in the nMIS region 1B and the pMIS region 1C and thus exposethe upper surface of the isolation region EI and the top surface of theinsulating film IF3 in the nMIS region 1B and the pMIS region 1C.Consequently, the upper and side surfaces of each of the fins FB and FCare partly exposed from the insulating film IF4 and the semiconductorfilm SI2. Thus, over each of the fins FB and FC, a dummy gate electrodeDG made of the semiconductor film SI2 is formed via the insulating filmIF3.

The dummy gate electrode DG is a film to be removed in the subsequentstep and replaced with a metal gate electrode, and does not remain inthe completed semiconductor device. In other words, the dummy gateelectrode DG is a pseudo gate electrode. Note that a description will begiven herein of the case where the insulating film IF3 covering the topsurface of each of the fins FB and FC exposed from the dummy gateelectrodes DG is removed. Then, a silicon oxide film is formed to coverthe side surfaces of the dummy gate electrodes DG, though theillustration thereof is omitted.

Next, as shown in FIG. 54, using the insulating films IF4 and IF5, thecontrol gate electrode CG2, the memory gate electrode MG, and the dummygate electrodes DG as a mask, ion implantation is performed on the uppersurface of each of the fins FA, FB, and FC. Thus, in the upper surfaceof each of the fins FA, the pair of extension regions EX1 as the n-typesemiconductor regions are formed. Also, in the upper surface of each ofthe fins FB, the pair of extension regions EX2 as the n-typesemiconductor regions are formed. Also, in the upper surface of each ofthe fins FC, the pair of extension regions EX3 as the p-typesemiconductor regions are formed.

At least the extension regions EX3 are formed in the step different fromthe step of forming the extension regions EX1 and EX2. The extensionregions EX1 and EX2 can be formed by implanting an n-type impurity(e.g., P (phosphorus) or As (arsenic)). The extension regions EX3 can beformed by implanting a p-type impurity (e.g., B (boron)).

Subsequently, over the semiconductor substrate SB, an insulating filmIF6 is formed using, e.g., a CVD method. The insulating film IF6 is madeof, e.g., a silicon nitride film. The insulating film IF6 covers therespective surfaces of the isolation region EI, the fins FA, FB, and FC,the control gate electrode CG2, the memory gate electrode MG, the dummygate electrode DG, and the insulating films IF4 and IF5.

Next, as shown in FIG. 55, a photoresist film PR3 is formed to exposethe nMIS region 1B and cover the memory cell region 1A and the pMISregion 1C. Then, using the photoresist film PR3 as a mask, dry etchingis performed to partly remove the insulating film IF6 in the nMIS region1B and thus expose the respective upper surfaces of the isolation regionEI, the fins FB, and the insulating film IF4. Over the side surfaces ofa multi-layer body including the dummy gate electrode DG and theinsulating film IF4 over the dummy gate electrode DG in the nMIS region1B, the sidewall spacers SW made of the insulating film IF6 are formed.

At this time, it may also be possible to form sidewalls made of theinsulating film IF6 over the side surfaces of each of the fins FB, butthe illustration of the sidewalls formed over the side surfaces of thefin FB is omitted in the drawing. Even in the case where sidewalls areformed over the respective side surfaces of the fins FA and FC, theillustration of the sidewalls is omitted.

Next, as shown in FIG. 56, using the photoresist film PR3, theinsulating film IF4, and the sidewall spacers SW as a mask, dry etchingis performed to retreat the upper surface of each of the fins FB exposedlateral to a pattern including the dummy gate electrode DG and thesidewall spacers SW in the nMIS region 1B. Thus, the upper surface ofthe fin FB exposed from the pattern is retreated to a position higherthan that of the upper surface of the isolation region EI and lower thanthat of the upper surface of the fin FB immediately below the dummy gateelectrode DG.

Next, as shown in FIG. 57, the photoresist film PR3 is removed. Then,using an epitaxial growth method, the epitaxial layers EP1 are formed tocover the upper and side surfaces of each of the fins FB which areexposed lateral to the pattern including the dummy gate electrode DG andthe sidewall spacers SW in the nMIS region 1B. The epitaxial layers EP1are made of, e.g., Si (silicon). It may also be possible herein to formthe epitaxial layers EP1 each made of, e.g., a SiP (silicon phosphide)film or a SiC (silicon carbide) film.

As described using FIG. 28, the epitaxial layers EP1 are thesemiconductor layers each having the rhomboidal cross-sectional shapeand covering the side surfaces of each of the fins FB in theY-direction. In FIG. 57, the epitaxial layers EP1 do not cover the sidesurfaces of the fin FB in the X-direction, but the epitaxial layers EP1may also cover the side surfaces. It is conceivable that, in the casewhere the side surfaces of the fin FB in the X-direction are coveredwith silicon oxide films or the like, the side surfaces are uncoveredwith the epitaxial layers EP1.

Next, as shown in FIG. 58, over the semiconductor substrate, aninsulating film IF7 made of, e.g., a silicon nitride film is formed. Theinsulating film IF7 can be formed using, e.g., a CVD method. In thememory cell region 1A and the pMIS region 1C, the insulating film IF7 isformed so as to cover the top surface of the insulating film IF6.However, in the drawing, the illustration of the insulating film IF7 inthe memory cell region 1A and the pMIS region 1C is omitted on theassumption that the insulating film IF7 is integrated with theinsulating film IF6.

Next, as shown in FIG. 59, a photoresist film PR4 is formed to exposethe pMIS region 1C and cover the memory cell region 1A and the nMISregion 1B. Then, using the photoresist film PR4 as a mask, dry etchingis performed to partly remove the insulating film IF6 in the pMIS region1C and thus expose the respective upper surfaces of the isolation regionEI, the fins FC, and the insulating film IF4. Over the side surfaces ofa multi-layer body including the dummy gate electrode DG and theinsulating film IF4 over the dummy gate electrode DG in the pMIS region1C, the sidewall spacers SW made of the insulating film IF6 are formed.

Next, as shown in FIG. 60, using the photoresist film PR4, theinsulating film IF4, and the sidewall spacers SW as a mask, dry etchingis performed to retreat the upper surface of each of the fins FC exposedlateral to a pattern including the dummy gate electrode DG and thesidewall spacers SW in the pMIS region 1C. Thus, the upper surface ofthe fin FC exposed from the pattern is retreated to a position higherthan that of the upper surface of the isolation region EI and lower thanthat of the upper surface of the fin FC immediately below the dummy gateelectrode DG.

Next, as shown in FIG. 61, the photoresist film PR4 is removed. Then,using an epitaxial growth method, the epitaxial layers EP2 are formed tocover the upper and side surfaces of each of the fins FC which areexposed lateral to the pattern including the dummy gate electrode DG andthe sidewall spacers SW in the pMIS region 1C. The epitaxial layers EP2are made of, e.g., SiGe (silicon germanium).

As described using FIG. 28, the epitaxial layers EP2 are thesemiconductor layers each having the rhomboidal cross-sectional shapeand covering the side surfaces of each of the fins FC in theY-direction. In FIG. 61, the epitaxial layers EP2 do not cover the sidesurfaces of the fin FC in the X-direction, but the epitaxial layers EP2may also cover the side surfaces. It is conceivable that, in the casewhere the side surfaces of the fin FC in the X-direction are coveredwith silicon oxide films or the like, the side surfaces are uncoveredwith the epitaxial layers EP2.

Next, as shown in FIG. 62, over the semiconductor substrate, aninsulating film IF8 made of, e.g., a silicon nitride film is formed. Theinsulating film IF8 can be formed using, e.g., a CVD method. Theinsulating film IF8 is formed so as to cover the top surface of theinsulating film IF6 in the memory cell region 1A and cover the topsurface of the insulating film IF7 in the nMIS region 1B. However, inthe drawing, the illustration of the insulating film IF8 in the memorycell region 1A and the nMIS region 1B is omitted on the assumption thatthe insulating film IF8 is integrated with the insulating film IF6 inthe memory cell region 1A and with the insulating film IF7 in the nMISregion 1B.

Next, as shown in FIG. 63, a photoresist film PR5 is formed to cover thenMIS region 1B and the pMIS region 1C and expose the memory cell region1A. Then, using the photoresist film PR5 as a mask, dry etching isperformed to partly remove the insulating film IF6 in the memory cellregion 1A and thus expose the respective upper surfaces of the isolationregion EI, the fins FA, and the insulating films IF4 and IF5. Over theside surfaces of a multi-layer body including the control gate electrodeCG2, the memory gate electrode MG, and the insulating films IF4 and IF5in the memory cell region 1A, the sidewall spacers SW made of theinsulating film IF6 are formed.

Next, as shown in FIG. 64, the photoresist film PR5 is removed. Then,using the insulating films IF4 and IF5, the dummy gate electrodes DG,the control gate electrode CG, the memory gate electrode MG, and thesidewall spacers SW as a mask, ion implantation is performed on theupper surfaces of the fins FA, FB, and FC. Thus, in the upper surface ofeach of the fins FA, the pair of diffusion regions D1 as the n-typesemiconductor regions are formed. In the upper surface of each of thefins FB, the pair of diffusion regions D2 as the n-type semiconductorregions are formed. In the upper surface of each of the fins FC, thepair of diffusion regions D3 as the p-type semiconductor regions areformed. In the nMIS region 1B and the pMIS region 1C, impurities areimplanted herein into the fins FB and FC through the insulating filmsIF7 and IF8.

At least the diffusion regions D3 are formed in the step different fromthe step of forming the diffusion regions D1 and D2. The diffusionregions D1 and D2 can be formed by implanting an n-type impurity (e.g.,P (phosphorus) or As (arsenic)). The diffusion regions D3 can be formedby implanting a p-type impurity (e.g., B (boron)). In the step offorming the diffusion regions D1 and D2, ion implantation is performedat an impurity concentration higher than that in the ion implantationstep performed when the extension regions EX1 and EX2 are formed. In thestep of forming the diffusion regions D3, ion implantation is performedat an impurity concentration higher than that in the ion implantationstep performed when the extension regions EX3 are formed.

Thus, the source and drain regions including the diffusion regions D1and the extension regions EX1, the source and drain regions includingthe diffusion regions D2 and the extension regions EX2, and the sourceand drain regions including the diffusion regions D3 and the extensionregions EX3 are formed. In this ion implantation step, the diffusionregions D2 are formed in both of the epitaxial layers EP1 and the fin FBlocated under the epitaxial layers EP1, while the diffusion regions D3are formed in both of the epitaxial layers EP2 and the fin FC locatedunder the epitaxial layers EP2.

In the memory cell region 1A, the source and drain regions and thecontrol gate electrode CG2 are included in the control transistor, whilethe source and drain regions and the memory gate electrode MG areincluded in the memory transistor. The control transistor and the memorytransistor are included in the memory cell MC2.

The diffusion regions D1 to D3 are formed herein after the formation ofthe epitaxial layers EP1 and EP2. However, the diffusion regions D2 mayalso be formed after the formation of, e.g., the sidewall spacers SWdescribed using FIG. 55 and before the etching step described using FIG.56. The diffusion regions D3 may also be formed after the formation of,e.g., the sidewall spacers SW described using FIG. 59 and before theetching step described using FIG. 60.

Next, as shown in FIG. 65, by a known salicide process, the silicidelayers S1 are formed to cover the source and drain regions formed ineach of the fins FA in the memory cell region 1A. The silicide layers S1formed herein cover the side and upper surfaces of the fin FA. In thenMIS region 1B and the pMIS region 1C, the fins FB and FC, the epitaxiallayers EP1 and EP2, and the like are covered with the insulating films(protective films) IF7 and IF8 so that the respective surfaces of thefins FB and FC and the epitaxial layers EP1 and EP2 are protected frombeing silicidized. The positions of the uppermost surfaces of thesilicide layers S1 are lower in level than those of the uppermostsurfaces of the epitaxial layers EP1 and EP2.

Subsequently, over the main surface of the semiconductor substrate SB, aliner film (not shown) made of, e.g., a silicon nitride film and theinterlayer insulating film IL1 made of a silicon oxide film are formedin this order. The liner film and the interlayer insulating film IL1 canbe formed by, e.g., a CVD method. The interlayer insulating film IL1 hasa thickness larger than the total height of each of the fins FA over theisolation region EI and a multi-layer body including the control gateelectrode CG2 and the insulating film IF4. Then, using, e.g., a CMPmethod, the upper surface of the interlayer insulating film IL1 isplanarized.

Next, as shown in FIG. 66, using, e.g., a CMP method, polishing isperformed on the upper surface of the interlayer insulating film IL1,the insulating films IF4 and IF5, and the sidewall spacers SW to exposethe respective upper surfaces of the dummy gate electrodes DG in thenMIS region 1B and the pMIS region 1C. Thus, the insulating films IF4and IF5 are removed to expose the respective upper surfaces of thecontrol gate electrode CG2 and the memory gate electrode MG.

Next, as shown in FIG. 67, the step of removing the dummy gate electrodeDG exposed in the pMIS region 1C is performed. Specifically, after ahard mask HM2 is formed over the semiconductor substrate SB by, e.g., aCVD method, using a photolithographic technique and an etching method,the hard mask HM2 is removed from the pMIS region 1C to expose the dummygate electrode DG in the pMIS region 1C. The hard mask HM2 is made of,e.g., a silicon oxide film or a TiN (titanium nitride) film. Therespective gate electrodes in the nMIS region 1B and the memory cellregion 1A are covered with the hard mask HM2.

Subsequently, the dummy gate electrode DG exposed from the hard mask HM2is removed by wet etching. The insulating film IF3 under the dummy gateelectrode DG is also removed herein, but the insulating film IF3 mayalso be left. Alternatively, after the insulating film IF3 is removed,an insulating film may also be formed to cover the bottom surface of atrench formed by removing the dummy gate electrode DG.

Next, as shown in FIG. 68, in the trench, the insulating film HK as thegate insulating film and the gate electrode G2 as the metal gateelectrode are formed. Specifically, first, over the semiconductorsubstrate SB including the hard mask HM2, the insulating film HK and themetal films MF5 and MF6 are formed in this order using, e.g., a CVDmethod and a sputtering method. The insulating film HK is a high-k filmhaving a dielectric constant higher than that of a silicon nitride film.The insulating film HK is made of a hafnium oxide film herein, but mayalso be formed of another metal oxide film such as a zirconium oxidefilm, an aluminum oxide film, a tantalum oxide film, or a lanthanumoxide film.

The metal film MF5 is made of a titanium nitride (TiN) film herein but,as the meta film MF5, a tantalum nitride (TaN) film, a tungsten nitride(WN) film, a titanium carbide (TiC) film, a tantalum carbide (TaC) film,a tungsten carbide (WC) film, a tantalum carbonitride (TaCN) film, atitanium (Ti) film, a tantalum (Ta) film, a titanium aluminum (TiAl)film, or the like may also be used instead. The metal film MF6 is madeof, e.g., an aluminum (Al) film.

The trench formed by removing the dummy gate electrode DG from the pMISregion 1C is completely filled with a multi-layer film including theinsulating film HK and the metal films MF5 and MF6. Then, the unneededfilms over the interlayer insulating film IL1 are removed by, e.g., aCMP method to expose the upper surface of the interlayer insulating filmIL1 in the pMIS region 1C and thus form the gate insulating film made ofthe insulating film HK embedded in the trench and the gate electrode G2including the metal films MF5 and MF6 embedded in the trench. Thus, thep-type transistor QP including the gate electrode G2 and the source anddrain regions in the pMIS region 1C is formed.

Next, as shown in FIG. 69, the step of removing the dummy gate electrodeDG exposed in the nMIS region 1B is performed. Specifically, the hardmask HM2 is removed, and subsequently a hard mask HM3 is formed over thesemiconductor substrate SB by, e.g., a CVD method. Then, using aphotolithographic technique and an etching method, the hard mask HM3 isremoved from the nMIS region 1B to expose the dummy gate electrode DG inthe nMIS region 1B. The hard mask HM3 is made of, e.g., a silicon oxidefilm or a TiN (titanium nitride) film. The respective gate electrodes inthe pMIS region 1C and the memory cell region 1A are covered with thehard mask HM3.

Subsequently, the dummy gate electrode DG exposed from the hard mask HM3is removed by wet etching. The insulating film IF3 under the dummy gateelectrode DG is also removed herein, but the insulating film IF3 mayalso be left. Alternatively, after the insulating film IF3 is removed,an insulating film may also be formed to cover the bottom surface of atrench formed by removing the dummy gate electrode DG.

Subsequently, in the trench, the insulating film HK as the gateinsulating film and the gate electrode G1 as the metal gate electrodeare formed. Specifically, first, over the semiconductor substrate SBincluding the hard mask HM3, using, e.g., a CVD method and a sputteringmethod, the insulating film HK and the metal films MF3 and MF4 areformed in this order. The insulating film HK is a high-k film having adielectric constant higher than that of a silicon nitride film. Theinsulating film HK is made of a hafnium oxide film herein, but may alsobe formed of another metal oxide film such as a zirconium oxide film, analuminum oxide film, a tantalum oxide film, or a lanthanum oxide film.

The metal film MF3 is made of a titanium aluminum (TiAl) film hereinbut, as the metal film MF3, a titanium nitride (TiN) film, a tantalumnitride (TaN) film, a tungsten nitride (WN) film, a titanium carbide(TiC) film, a tantalum carbide (TaC) film, a tungsten carbide (WC) film,a tantalum carbonitride (TaCN) film, a titanium (Ti) film, a tantalum(Ta) film, or the like may also be used instead. The metal film MF4 ismade of, e.g., an aluminum (Al) film.

The trench formed by removing the dummy gate electrode DG from the nMISregion 1B is completely filled with a multi-layer film including theinsulating film HK and the metal films MF3 and MF4. Then, the unneededfilms over the interlayer insulating film IL1 are removed by, e.g., aCMP method to expose the upper surface of the interlayer insulating filmIL1 in the nMIS region 1B and thus form the gate insulating film made ofthe insulating film HK embedded in the trench and the gate electrode G1including the metal films MF3 and MF4 embedded in the trench. Thus, then-type transistor QN including the gate electrode G1 and the source anddrain regions in the nMIS region 1B is formed.

Next, as shown in FIG. 70, the hard mask HM3 is removed and,subsequently, the insulating film IF9 is formed over the semiconductorsubstrate SB by, e.g., a CVD method. Then, using a photolithographictechnique and an etching method, the insulating film IF9 is removed fromthe memory cell region 1A. As a result, the gate electrodes G1 and G2 inthe nMIS region 1B and the pMIS region 1C are covered with theinsulating film IF9, but the control gate electrode CG2 and the memorygate electrode MG are exposed from the insulating film IF9.

Subsequently, a known salicide process is performed to form the silicidelayers S2 in the respective upper surfaces of the control gate electrodeCG2 and the memory gate electrode MG. The silicide layers S1 and S2 aremade of the same material.

Next, as shown in FIG. 71, using, e.g., a CVD method, over thesemiconductor substrate SB including the insulating film IF9, theinterlayer insulating film IL2 is formed. The interlayer insulating filmIL2 is made of, e.g., a silicon oxide film. Subsequently, the uppersurface of the interlayer insulating film IL2 is planarized by a CMPmethod or the like. Subsequently, using a photolithographic techniqueand a dry etching method, the plurality of contact holes CH are formedto extend through the interlayer insulating films IL2 and IL1. Notethat, in the nMIS region 1B and the pMIS region 1C, the contact holes CHalso extend through the insulating film IF9.

In the memory cell region 1A, at the bottom portions of the contactholes CH, the upper surfaces of the silicide layers S1 immediately abovethe source and drain regions are partly exposed. In the nMIS region 1B,at the bottom portions of the contact holes CH, the upper surfaces ofthe epitaxial layers EP1 as the portions of the source and drain regionsare partly exposed. In the pMIS region 1C, at the bottom portions of thecontact holes CH, the upper surfaces of the epitaxial layers EP2 as theportions of the source and drain regions are partly exposed.

In the region which is not illustrated, the contact holes CH are formedto partly expose the respective upper surfaces of the gate electrodes G1and G2, the control gate electrode CG2, and the memory gate electrodeMG. These contact holes CH do not extend through the interlayerinsulating film IL1. In a direction perpendicular to the main surface ofthe semiconductor substrate SB, the lengths of the contact holes CHimmediately above the epitaxial layers EP1 and EP2 are smaller than thelengths of the contact holes CH immediately above the silicide layersS1.

Next, as shown in FIG. 72, using a known salicide process, over therespective upper surfaces of the epitaxial layers EP1 and EP2 exposed atthe bottom portions of the contact holes CH in the nMIS region 1B andthe pMIS region 1C, the silicide layers S3 are formed. Specifically,over the main surface of the semiconductor substrate SB including theinner portions of the contact holes CH, using, e.g., a CVD method, ametal film is formed. Then, heat treatment is performed to cause themetal film to react with the respective upper surfaces of the epitaxiallayers EP1 and EP2 to form the silicide layers S3 at the bottom portionsof the contact holes CH. Then the metal film is removed.

Since it is difficult herein to form a metal film in such thin openingsas the contact holes CH by a sputtering method, the foregoing metal filmis formed by a CVD method. However, since a Ni (nickel) film is hard toform by the CVD method, a Ti (titanium) film which is easy to form bythe CVD method is formed as the metal film. Consequently, the silicidelayers S3 are made of a TiSi₂ (titanium silicide) film. In other words,the silicide layers S3 are made of the material different from thematerials of the silicide layers S1 and S2. Note that, in the step offorming the silicide layers S3, the Ti (titanium) film may also be leftat the bottom portions of the contact holes CH immediately above thesilicide layers S1 in the memory cell region 1A.

Next, as shown in FIG. 73, in the contact holes CH, the conductive plugsPG1 and PG2 made of tungsten (W) or the like are formed as the couplingconductive members. Each of the plugs PG1 and PG2 has a multi-layerstructure including a barrier conductor film (e.g., a titanium film, atitanium nitride film, or a multi-layer film thereof) and a mainconductor film (e.g., a tungsten film) located over the barrierconductor film.

The plugs PG1 are electrically coupled to the source region and thedrain region of the memory cell MC2 via the silicide layers S1. In thecase where the Ti films remain over the silicide layers S1 as describedabove, the Ti films are interposed between the plugs PG1 and thesilicide layers S1. The plugs PG2 are embedded in the contact holes CHin the nMIS region 1B and electrically coupled to the epitaxial layersEP1 via the silicide layers S3. Thus, the plugs PG2 are electricallycoupled to the source and drain regions of the n-type transistor QN. Theplugs PG2 are embedded in the contact holes CH in the pMIS region 1C andelectrically coupled to the epitaxial layers EP2 via the silicide layersS3. Thus, the plugs PG2 are electrically coupled to the source and drainregions of the p-type transistor QP.

In a direction perpendicular to the main surface of the semiconductorsubstrate SB, the lengths of the contact holes CH immediately above theepitaxial layers EP1 and EP2 are smaller than the lengths of the contactholes CH immediately above the silicide layers S1. This is because theheights of the upper surfaces of the silicide layers S1 from the mainsurface of the semiconductor substrate SB are lower than the heights ofthe upper surfaces of the epitaxial layers EP1 and EP2 from the mainsurface of the semiconductor substrate SB.

The reason why the heights of the upper surfaces of the epitaxial layersEP1 and EP2 are higher than the heights of the upper surfaces of thesilicide layers S1 is that the epitaxial layers EP1 and EP2 are formedto have large volumes and thus reduce the resistances of the source anddrain regions of each of the n-type transistor QN and the p-typetransistor QP. Specifically, since the silicide layers S1 in the memorycell region 1A are made of a material having a resistance value lowerthan that of a semiconductor layer, even when the volumes and thicknessthereof are not large, it is possible to satisfactorily reduce theresistances of the source and drain regions of the memory cell MC2.

By contrast, the resistances of the epitaxial layers EP1 and EP2 arehigher than those of the silicide layers S1. Accordingly, to reduce theresistances of the source and drain regions of each of the n-typetransistor QN and the p-type transistor QP, it is necessary for theepitaxial layers EP1 and EP2 to have volumes and thicknesses larger thanthose of the silicide layers S1. In other words, by forming theepitaxial layers EP1 and EP2 such that the heights of the respectiveupper surfaces thereof are higher than the heights of the upper surfacesof the silicide layers S1, it is possible to reduce the resistances ofthe source and drain regions of each of the n-type transistor QN and thep-type transistor QP.

Note that, in the case where the metal film (titanium film) deposited toform the silicide layers S3 remains at the bottom portions of thecontact holes CH over the silicide layers S1, the Ti (titanium) filmsare interposed between the upper surfaces of the silicide layers S1 andthe plugs PG1.

Next, as shown in FIG. 74, over the interlayer insulating film IL2, thewires M1 are formed. Each of the wires M1 is made of a multi-layerstructure including a barrier conductor film (such as, e.g., a titaniumnitride film, a tantalum film, or a tantalum nitride film) and a mainconductor film (copper film) formed over the barrier conductor film. InFIG. 3, for simpler illustration, the barrier conductor film and themain conductor film are integrally shown as each of the wires M1. Thesame applies also to the plugs PG1 and PG2.

The wires M1 can be formed by, e.g., a so-called single damascenemethod. Specifically, by forming an interlayer insulating film havingwire trenches over the interlayer insulating film IL2 and embedding ametal film in the wire trenches, the wires M1 can be formed. However,the illustration of the interlayer insulating film located lateral tothe wires M1 is omitted herein.

<Effects of Manufacturing Method of Semiconductor Device>

Next, a description will be given of the method of manufacturing thesemiconductor device in the present second embodiment.

From the manufacturing method of the semiconductor device in the presentsecond embodiment, the same effects as obtained from the manufacturingmethod of the semiconductor device in the foregoing first embodiment canbe obtained. Specifically, since the paraelectric film HK1 is formed asthe interfacial layer (block layer) between the ferroelectric film HK2and the semiconductor substrate SB (fin FA), it is possible to preventthe electric field induced in the ferroelectric film HK2 from causingdielectric breakdown of the interfacial layer. Therefore, it is possibleto improve the reliability of the semiconductor device.

Also, in the present second embodiment, as described using FIG. 3, thecrystals GR2 in the ferroelectric film HK2 are formed larger than thecrystals GR1 in the paraelectric film HK1 to allow the residualpolarization in the ferroelectric film HK2 to be increased. This canreduce the operating voltage of the ferroelectric memory and improve theinformation retention property of the ferroelectric memory. Therefore,it is possible to improve the performance of the semiconductor device.Since the paraelectric film HK1 is formed herein as the interfaciallayer in contact with the lower surface of the ferroelectric film HK2,the crystals GR2 can be formed larger than the crystals GR1.

Also, in the present second embodiment, in the step described using FIG.47, the ferroelectric film HK2 is formed using a microwave.Specifically, in the second heat treatment described using FIGS. 12 and13, heating is performed using the microwave having the electric fieldwhich vibrates in the direction perpendicular to the main surface of thesemiconductor substrate SB. This allows an orthorhombic crystal which ispolarized in the perpendicular direction to be grown in theferroelectric film HK2. In other words, it is possible to prevent acrystal which is polarized in a direction other than the perpendiculardirection from growing in the ferroelectric film HK2. As a result, theplurality of crystals included in the ferroelectric film HK2 arepolarized in equal directions to allow the residual polarization in theferroelectric film HK2 to be increased.

By performing the second heat treatment using the microwave, it ispossible to achieve crystallization at a low temperature of not morethan 400° C. and increase the likelihood of formation of an orthorhombiccrystal in the ferroelectric film HK2 formed thereby. In other words, byincreasing the ratio of the orthorhombic crystals to all the crystalsincluded in the ferroelectric film HK2, it is possible to increase theresidual polarization in the ferroelectric film HK2.

By performing the second heat treatment with the metal film MF1 beingformed over the high-k film AM2 (see FIG. 11), it is possible toincrease the likelihood of formation of the orthorhombic crystal in theferroelectric film HK2.

As described above, by increasing the likelihood of formation of theorthorhombic crystal in the ferroelectric film HK2, it is possible toenhance the polarization performance of the ferroelectric film HK2.Briefly, even when the voltage applied to the control gate electrode CG1of the memory cell MC2 is low, the ferroelectric film HK2 can bepolarized to allow a reduction in the power consumption of theferroelectric memory. In addition, the increased residual polarizationallows an improvement in retention property. Therefore, it is possibleto improve the performance of the semiconductor device.

While the invention achieved by the present inventors has beenspecifically described heretofore on the basis of the embodimentsthereof, the present invention is not limited to the foregoingembodiments. It will be appreciated that various changes andmodifications can be made in the invention within the scope notdeparting from the gist thereof.

For example, in each of the foregoing first and second embodiments, thedescription has been given of the memory cell including the n-typetransistor, but the transistor may also be formed as a p-typetransistor. In that case, the conductivity types of the well, the sourceand drain regions, and the like each included in the transistor mayappropriately be inverted.

Each of the first and second modifications of the foregoing firstembodiment is also applicable to the foregoing second embodiment.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor substrate; a first insulating film formed over thesemiconductor substrate; a ferroelectric film formed over the firstinsulating film; and a first gate electrode formed over theferroelectric film, wherein the ferroelectric film comprises a firsthafnium oxide film, wherein the first insulating film has a dielectricconstant higher than that of silicon nitride, and wherein the firstinsulating film is a paraelectric film comprising a second hafnium oxidefilm.
 2. The semiconductor device according to claim 1, furthercomprising: source and drain regions formed in an upper surface of thesemiconductor substrate such that the first gate electrode is interposedtherebetween.
 3. The semiconductor device according to claim 1, whereinthe ferroelectric film has a thickness larger than that of the firstinsulating film.
 4. The semiconductor device according to claim 1,wherein an average grain diameter of a plurality of first crystalsincluded in the ferroelectric film is larger than an average graindiameter of a plurality of second crystals included in the firstinsulating film.
 5. The semiconductor device according to claim 1,wherein an upper surface of the ferroelectric film has unevenness largerthan that of an upper surface of the first insulating film.
 6. Thesemiconductor device according to claim 1, wherein the ferroelectricfilm and the first insulating film comprise the same material.
 7. Thesemiconductor device according to claim 6, wherein the ferroelectricfilm comprises a first crystal having an orthorhombic crystal phase,while the first insulating film comprises a second crystal having anon-orthorhombic crystal phase.
 8. The semiconductor device according toclaim 1, wherein the first insulating film has an impurity concentrationlower than that of the ferroelectric film.
 9. The semiconductor deviceaccording to claim 1, wherein, between the ferroelectric film and thefirst gate electrode, a metal film is additionally formed.
 10. Thesemiconductor device according to claim 2, further comprising: a secondgate electrode provided over the upper surface of the semiconductorsubstrate via a second insulating film to be adjacent to one sidesurface of the first gate electrode via the first insulating film andthe ferroelectric film, wherein the first gate electrode, the secondgate electrode, and the source and drain regions are included in anonvolatile storage element.
 11. The semiconductor device according toclaim 10, further comprising: a protruding portion which is a portion ofthe semiconductor substrate protruding from the upper surface of thesemiconductor substrate and extending in a first direction along theupper surface of the semiconductor substrate, wherein each of the firstgate electrode and the second gate electrode extends in a seconddirection orthogonal to the first direction, and wherein the source anddrain regions are formed in a top surface of the protruding portion suchthat a pattern including the first gate electrode and the second gateelectrode is interposed therebetween in the first direction.